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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-10-18 10:18:12 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-11-23 04:59:50 +0000 |
| commit | 46234ea36be69b89c42b550838092ecc0f0bf972 (patch) | |
| tree | e0136c0c4e31a8b3638b7979f223d1026075dbd6 /src/southbridge/intel | |
| parent | f1c8ede1a5bcf26f938b3f5a8cfefa8acd156505 (diff) | |
| download | coreboot-46234ea36be69b89c42b550838092ecc0f0bf972.tar.xz | |
sb/intel/i82801jx: Store initial timestamp in bootblock
The function to fetch this timestamp is already present.
Change-Id: I760aea8a867339764be9ca627b2ccdff4fd18e30
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/i82801jx/bootblock.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c index cc685c4544..115555c599 100644 --- a/src/southbridge/intel/i82801jx/bootblock.c +++ b/src/southbridge/intel/i82801jx/bootblock.c @@ -14,8 +14,21 @@ */ #include <arch/io.h> +#include <cpu/x86/tsc.h> #include "i82801jx.h" +static void store_initial_timestamp(void) +{ + /* + * We have two 32bit scratchpad registers available: + * D0:F0 0xdc (SKPAD) + * D31:F2 0xd0 (SATA SP) + */ + tsc_t tsc = rdtsc(); + pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo); + pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi); +} + static void enable_spi_prefetch(void) { u8 reg8; @@ -31,6 +44,7 @@ static void enable_spi_prefetch(void) static void bootblock_southbridge_init(void) { + store_initial_timestamp(); enable_spi_prefetch(); /* Enable RCBA */ |