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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-03-24 14:59:45 +0100 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2019-04-13 14:49:19 +0000 |
| commit | a3caa2d3bbe791c39af2b56ae6f94ec83c4e09e2 (patch) | |
| tree | c52cb29538fd396629901ff4b4540290bc612325 /src/southbridge/intel | |
| parent | 0168639b9af184097dcfd913a29f970eaaa8a47e (diff) | |
| download | coreboot-a3caa2d3bbe791c39af2b56ae6f94ec83c4e09e2.tar.xz | |
sb/intel/lynxpoint: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB
Use common code to detect ACPI S3.
Untested.
Change-Id: I87ac56e4ba1fb83761786d5f32a0fc308ee9718a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32039
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/Kconfig | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/early_pch.c | 23 |
2 files changed, 3 insertions, 21 deletions
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 87e197070b..431744f08c 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -26,6 +26,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select SOUTHBRIDGE_INTEL_COMMON_FINALIZE + select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select IOAPIC select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 994021c6b0..3d2d2c48fa 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -19,6 +19,7 @@ #include <device/pci_ops.h> #include <device/device.h> #include <device/pci_def.h> +#include <southbridge/intel/common/pmclib.h> #include <elog.h> #include "pch.h" #include "chip.h" @@ -67,26 +68,6 @@ static void pch_generic_setup(void) printk(BIOS_DEBUG, " done.\n"); } -static int sleep_type_s3(void) -{ - u32 pm1_cnt; - u16 pm1_sts; - int is_s3 = 0; - - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - if (pm1_sts & WAK_STS) { - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); - if (((pm1_cnt >> 10) & 7) == SLP_TYP_S3) { - /* Clear SLP_TYPE. */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); - is_s3 = 1; - } - } - return is_s3; -} - void pch_enable_lpc(void) { const struct device *dev = pcidev_on_root(0x1f, 0); @@ -148,7 +129,7 @@ int early_pch_init(const void *gpio_map, /* Mainboard RCBA settings */ pch_config_rcba(rcba_config); - wake_from_s3 = sleep_type_s3(); + wake_from_s3 = southbridge_detect_s3_resume(); #if CONFIG(ELOG_BOOT_COUNT) if (!wake_from_s3) |