summaryrefslogtreecommitdiff
path: root/src/southbridge/intel
diff options
context:
space:
mode:
authorVladimir Serbinenko <phcoder@gmail.com>2015-05-21 10:32:59 +0200
committerVladimir Serbinenko <phcoder@gmail.com>2015-05-29 11:26:06 +0200
commitb06a249c3b766531ca247bb1278d34875f0d86e4 (patch)
tree1391e4ac2d85045e0eb80c423a4af53c44aad580 /src/southbridge/intel
parent501cce8b181500bab8a6f6e8634ac8bb45abfd1c (diff)
downloadcoreboot-b06a249c3b766531ca247bb1278d34875f0d86e4.tar.xz
bd82x6x: Move calling of finalize() on resume to southbridge code
Change-Id: I6416cd5780fbda0b3c2e236ce98a9f9a508e70c6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10293 Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 842d9d994f..c1bc45fdaf 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -805,6 +805,14 @@ static void southbridge_fill_ssdt(void)
intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);
}
+static void lpc_final(struct device *dev)
+{
+ if (CONFIG_HAVE_SMI_HANDLER && acpi_is_wakeup_s3()) {
+ /* Call SMM finalize() handlers before resume */
+ outb(0xcb, 0xb2);
+ }
+}
+
static struct pci_operations pci_ops = {
.set_subsystem = set_subsystem,
};
@@ -817,6 +825,7 @@ static struct device_operations device_ops = {
.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
.acpi_fill_ssdt_generator = southbridge_fill_ssdt,
.init = lpc_init,
+ .final = lpc_final,
.enable = pch_lpc_enable,
.scan_bus = scan_static_bus,
.ops_pci = &pci_ops,