coreboot has 13 instances of IOAPIC setup distributed across a lot

of components. This patch is a rewrite of the generic IOAPIC setup code.
Additionally it drops the other 12 instances of IOAPIC setup code and
makes the components use the generic code.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 25 insertions, 241 deletions

diff --git a/src/southbridge/intel/esb6300/esb6300_lpc.c b/src/southbridge/intel/esb6300/esb6300_lpc.c
index bae9e715d5..09caeb729f 100644
--- a/src/southbridge/intel/esb6300/esb6300_lpc.c
+++ b/src/southbridge/intel/esb6300/esb6300_lpc.c
@@ -9,6 +9,7 @@
 #include <pc80/mc146818rtc.h>
 #include <pc80/isa-dma.h>
 #include <arch/io.h>
+#include <arch/ioapic.h>
 #include "esb6300.h"
 
 #define ACPI_BAR 0x40
@@ -22,52 +23,6 @@
 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
 #endif
 
-#define ALL		(0xff << 24)
-#define NONE		(0)
-#define DISABLED	(1 << 16)
-#define ENABLED		(0 << 16)
-#define TRIGGER_EDGE	(0 << 15)
-#define TRIGGER_LEVEL	(1 << 15)
-#define POLARITY_HIGH	(0 << 13)
-#define POLARITY_LOW	(1 << 13)
-#define PHYSICAL_DEST	(0 << 11)
-#define LOGICAL_DEST	(1 << 11)
-#define ExtINT		(7 << 8)
-#define NMI		(4 << 8)
-#define SMI		(2 << 8)
-#define INT		(1 << 8)
-
-static void setup_ioapic(device_t dev)
-{
-	int i;
-	unsigned long value_low, value_high;
-	unsigned long ioapic_base = 0xfec00000;
-	volatile unsigned long *l;
-	unsigned interrupts;
-
-	l = (unsigned long *) ioapic_base;
-
-	l[0] = 0x01;
-	interrupts = (l[04] >> 16) & 0xff;
-	for (i = 0; i < interrupts; i++) {
-		l[0] = (i * 2) + 0x10;
-		l[4] = DISABLED;
-		value_low = l[4];
-		l[0] = (i * 2) + 0x11;
-		l[4] = NONE; /* Should this be an address? */
-		value_high = l[4];
-		if (value_low == 0xffffffff) {
-			printk_warning("%d IO APIC not responding.\n",
-				dev_path(dev));
-			return;
-		}
-	}
-
-	/* Put the ioapic in virtual wire mode */
-	l[0] = 0 + 0x10;
-	l[4] = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
-}
-
 #define SERIRQ_CNTL 0x64
 static void esb6300_enable_serial_irqs(device_t dev)
 {
@@ -287,7 +242,7 @@ static void lpc_init(struct device *dev)
 	value |= (1 << 8)|(1<<7);
 	value |= (6 << 0)|(1<<13)|(1<<11);
 	pci_write_config32(dev, 0xd0, value);
-	setup_ioapic(dev);
+	setup_ioapic(0xfec00000, 0); // don't rename IO APIC ID
 
 	/* disable reset timer */
 	pci_write_config8(dev, 0xd4, 0x02);
diff --git a/src/southbridge/intel/esb6300/esb6300_pic.c b/src/southbridge/intel/esb6300/esb6300_pic.c
index 97635ae524..9d02536cd4 100644
--- a/src/southbridge/intel/esb6300/esb6300_pic.c
+++ b/src/southbridge/intel/esb6300/esb6300_pic.c
@@ -6,50 +6,9 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
+#include <arch/ioapic.h>
 #include "esb6300.h"
 
-#define ALL		(0xff << 24)
-#define NONE		(0)
-#define DISABLED	(1 << 16)
-#define ENABLED		(0 << 16)
-#define TRIGGER_EDGE	(0 << 15)
-#define TRIGGER_LEVEL	(1 << 15)
-#define POLARITY_HIGH	(0 << 13)
-#define POLARITY_LOW	(1 << 13)
-#define PHYSICAL_DEST	(0 << 11)
-#define LOGICAL_DEST	(1 << 11)
-#define ExtINT		(7 << 8)
-#define NMI		(4 << 8)
-#define SMI		(2 << 8)
-#define INT		(1 << 8)
-
-static void setup_ioapic(device_t dev)
-{
-	int i;
-	unsigned long value_low, value_high;
-	unsigned long ioapic_base = 0xfec10000;
-	volatile unsigned long *l;
-	unsigned interrupts;
-
-	l = (unsigned long *) ioapic_base;
-
-	l[0] = 0x01;
-	interrupts = (l[04] >> 16) & 0xff;
-	for (i = 0; i < interrupts; i++) {
-		l[0] = (i * 2) + 0x10;
-		l[4] = DISABLED;
-		value_low = l[4];
-		l[0] = (i * 2) + 0x11;
-		l[4] = NONE; /* Should this be an address? */
-		value_high = l[4];
-		if (value_low == 0xffffffff) {
-			printk_warning("%s IO APIC not responding.\n", 
-				dev_path(dev));
-			return;
-		}
-	}
-}
-
 static void pic_init(struct device *dev)
 {
 
@@ -64,7 +23,7 @@ static void pic_init(struct device *dev)
 	pci_write_config8(dev, 0x3c, 0xff);
 
 	/* Setup the ioapic */
-	setup_ioapic(dev);
+	clear_ioapic(0xfec10000);
 }
 
 static void pic_read_resources(device_t dev)
diff --git a/src/southbridge/intel/i3100/i3100_lpc.c b/src/southbridge/intel/i3100/i3100_lpc.c
index a2d858ef17..e516939fe9 100644
--- a/src/southbridge/intel/i3100/i3100_lpc.c
+++ b/src/southbridge/intel/i3100/i3100_lpc.c
@@ -29,6 +29,7 @@
 #include <pc80/mc146818rtc.h>
 #include <pc80/isa-dma.h>
 #include <arch/io.h>
+#include <arch/ioapic.h>
 #include "i3100.h"
 
 #define ACPI_BAR 0x40
@@ -49,60 +50,6 @@
 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
 #endif
 
-#define ALL		(0xff << 24)
-#define NONE		(0)
-#define DISABLED	(1 << 16)
-#define ENABLED		(0 << 16)
-#define TRIGGER_EDGE	(0 << 15)
-#define TRIGGER_LEVEL	(1 << 15)
-#define POLARITY_HIGH	(0 << 13)
-#define POLARITY_LOW	(1 << 13)
-#define PHYSICAL_DEST	(0 << 11)
-#define LOGICAL_DEST	(1 << 11)
-#define ExtINT		(7 << 8)
-#define NMI		(4 << 8)
-#define SMI		(2 << 8)
-#define INT		(1 << 8)
-
-static void setup_ioapic(device_t dev)
-{
-	int i;
-	u32 value_low, value_high;
-	u32 ioapic_base = 0xfec00000;
-	volatile u32 *l;
-	u32 interrupts;
-	struct resource *res;
-
-	/* Enable IO APIC */
-	res = find_resource(dev, RCBA);
-	if (!res) {
-		return;
-	}
-	*((u8 *)(res->base + 0x31ff)) |= (1 << 0);
-
-	l = (u32 *) ioapic_base;
-
-	l[0] = 0x01;
-	interrupts = (l[04] >> 16) & 0xff;
-	for (i = 0; i < interrupts; i++) {
-		l[0] = (i * 2) + 0x10;
-		l[4] = DISABLED;
-		value_low = l[4];
-		l[0] = (i * 2) + 0x11;
-		l[4] = NONE; /* Should this be an address? */
-		value_high = l[4];
-		if (value_low == 0xffffffff) {
-			printk_warning("%d IO APIC not responding.\n",
-				dev_path(dev));
-			return;
-		}
-	}
-
-	/* Put the APIC in virtual wire mode */
-	l[0] = 0x12;
-	l[4] = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
-}
-
 static void i3100_enable_serial_irqs(device_t dev)
 {
 	/* set packet length and toggle silent mode bit */
@@ -363,7 +310,19 @@ static void i3100_gpio_init(device_t dev)
 
 static void lpc_init(struct device *dev)
 {
-	setup_ioapic(dev);
+	struct resource *res;
+
+	/* Enable IO APIC */
+	res = find_resource(dev, RCBA);
+	if (!res) {
+		return;
+	}
+	*((u8 *)(res->base + 0x31ff)) |= (1 << 0);
+
+	// TODO this code sets int 0 of the IOAPIC in Virtual Wire Mode
+	// (register 0x10/0x11) while the old code used int 1 (register 0x12)
+	// ... Why? 
+	setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IOAPIC ID
 
 	/* Decode 0xffc00000 - 0xffffffff to fwh idsel 0 */
 	pci_write_config32(dev, 0xd0, 0x00000000);
diff --git a/src/southbridge/intel/i82801er/i82801er_lpc.c b/src/southbridge/intel/i82801er/i82801er_lpc.c
index 943356c2c1..357e181a9d 100644
--- a/src/southbridge/intel/i82801er/i82801er_lpc.c
+++ b/src/southbridge/intel/i82801er/i82801er_lpc.c
@@ -9,6 +9,7 @@
 #include <pc80/mc146818rtc.h>
 #include <pc80/isa-dma.h>
 #include <arch/io.h>
+#include <arch/ioapic.h>
 #include "i82801er.h"
 
 #define ACPI_BAR 0x40
@@ -22,51 +23,6 @@
 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
 #endif
 
-#define ALL		(0xff << 24)
-#define NONE		(0)
-#define DISABLED	(1 << 16)
-#define ENABLED		(0 << 16)
-#define TRIGGER_EDGE	(0 << 15)
-#define TRIGGER_LEVEL	(1 << 15)
-#define POLARITY_HIGH	(0 << 13)
-#define POLARITY_LOW	(1 << 13)
-#define PHYSICAL_DEST	(0 << 11)
-#define LOGICAL_DEST	(1 << 11)
-#define ExtINT		(7 << 8)
-#define NMI		(4 << 8)
-#define SMI		(2 << 8)
-#define INT		(1 << 8)
-
-static void setup_ioapic(void)
-{
-	int i;
-	unsigned long value_low, value_high;
-	unsigned long ioapic_base = 0xfec00000;
-	volatile unsigned long *l;
-	unsigned interrupts;
-
-	l = (unsigned long *) ioapic_base;
-
-	l[0] = 0x01;
-	interrupts = (l[04] >> 16) & 0xff;
-	for (i = 0; i < interrupts; i++) {
-		l[0] = (i * 2) + 0x10;
-		l[4] = DISABLED;
-		value_low = l[4];
-		l[0] = (i * 2) + 0x11;
-		l[4] = NONE; /* Should this be an address? */
-		value_high = l[4];
-		if (value_low == 0xffffffff) {
-			printk_warning("IO APIC not responding.\n");
-			return;
-		}
-	}
-
-	/* Put the ioapic in virtual wire mode */
-	l[0] = 0 + 0x10;
-	l[4] = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
-}
-
 #define SERIRQ_CNTL 0x64
 static void i82801er_enable_serial_irqs(device_t dev)
 {
@@ -292,7 +248,7 @@ static void lpc_init(struct device *dev)
 	value = pci_read_config32(dev, 0xd4);
 	value |= (1<<1);
 	pci_write_config32(dev, 0xd4, value);
-	setup_ioapic();
+	setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IO APIC ID.
 
 	i82801er_enable_serial_irqs(dev);
 
diff --git a/src/southbridge/intel/pxhd/pxhd_bridge.c b/src/southbridge/intel/pxhd/pxhd_bridge.c
index 5913063606..1a21a9c03e 100644
--- a/src/southbridge/intel/pxhd/pxhd_bridge.c
+++ b/src/southbridge/intel/pxhd/pxhd_bridge.c
@@ -8,6 +8,7 @@
 #include <device/pci_ops.h>
 #include <device/pcix.h>
 #include <pc80/mc146818rtc.h>
+#include <arch/ioapic.h>
 #include <delay.h>
 #include "pxhd.h"
 
@@ -159,63 +160,17 @@ static const struct pci_driver pcix_driver2 __pci_driver = {
         .device = 0x032a,
 };
 
-#define ALL		(0xff << 24)
-#define NONE		(0)
-#define DISABLED	(1 << 16)
-#define ENABLED		(0 << 16)
-#define TRIGGER_EDGE	(0 << 15)
-#define TRIGGER_LEVEL	(1 << 15)
-#define POLARITY_HIGH	(0 << 13)
-#define POLARITY_LOW	(1 << 13)
-#define PHYSICAL_DEST	(0 << 11)
-#define LOGICAL_DEST	(1 << 11)
-#define ExtINT		(7 << 8)
-#define NMI		(4 << 8)
-#define SMI		(2 << 8)
-#define INT		(1 << 8)
-	/* IO-APIC virtual wire mode configuration */
-	/* mask, trigger, polarity, destination, delivery, vector */
-
-static void setup_ioapic(device_t dev)
-{
-	int i;
-	unsigned long value_low, value_high;
-	unsigned long ioapic_base;
-	volatile unsigned long *l;
-	unsigned interrupts;
-
-	ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-	l = (unsigned long *) ioapic_base;
-
-	/* Enable front side bus delivery */
-	l[0] = 0x03;
-	l[4] = 1;
-
-	l[0] = 0x01;
-	interrupts = (l[04] >> 16) & 0xff;
-	for (i = 0; i < interrupts; i++) {
-		l[0] = (i * 2) + 0x10;
-		l[4] = DISABLED;
-		value_low = l[4];
-		l[0] = (i * 2) + 0x11;
-		l[4] = NONE; /* Should this be an address? */
-		value_high = l[4];
-		if (value_low == 0xffffffff) {
-			printk_warning("IO APIC not responding.\n");
-			return;
-		}
-	}
-}
-
 static void ioapic_init(device_t dev)
 {
-	uint32_t value;
+	uint32_t value, ioapic_base;
 	/* Enable bus mastering so IOAPICs work */
 	value = pci_read_config16(dev, PCI_COMMAND);
 	value |= PCI_COMMAND_MASTER;
 	pci_write_config16(dev, PCI_COMMAND, value);
 
-	setup_ioapic(dev);
+	ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+
+	setup_ioapic(ioapic_base, 0); // Don't rename IOAPIC ID
 }
 
 static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)