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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-14 18:42:00 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-17 15:02:28 +0000 |
| commit | 2878c0b6dcc4d0dd9e0823cb63e9258f8b3655dc (patch) | |
| tree | b41f8b064bb40d107f32486a2cb13a7b49eee45a /src/southbridge/intel | |
| parent | b572c9d5e553c0cefc9d2f43c924430324a6eaaf (diff) | |
| download | coreboot-2878c0b6dcc4d0dd9e0823cb63e9258f8b3655dc.tar.xz | |
nb/intel/nehalem: use pmclib to detect S3 resume
During the raminit the CPU gets reset, so reprogram those bits in
PM1_CNT such that the CPU remains aware that this is a S3 resume path
after the reset.
Change-Id: I8f5cafa235c8ab0d0a59fbeeee3465ebca4cc5d0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/ibexpeak/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 53240cb1df..5757a49a50 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -33,6 +33,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_SMM + select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select HAVE_USBDEBUG_OPTIONS select COMMON_FADT select ACPI_SATA_GENERATOR |