sb/intel/bd82x6x: Add and use more RCBA defines

Taken from
"Intel 6 Series Chipset and Intel C200 Series Chipset"
Document Number: 324645-006 and
"Intel 5 Series Chipset and Intel 3400 Series Chipset"
Document Number: 322169-004 and
"Intel 6 Series Chipset"
Document Number: 324645-001.

UPDCR was found in GNU/Linux's drivers/pci/quirks.c.
DMC2 was guessed as it's close to DMC and defined for 5 series chipset.

Test:
Run BUILD_TIMELESS=1 and compared the coreboot.roms, no differences.

Change-Id: I4fed7c38078cabd4308424c7547416e87c9e6fa7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

7 files changed, 176 insertions, 115 deletions

diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index 8d424b8ba6..e3379d6af0 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -242,11 +242,11 @@ static void azalia_init(struct device *dev)
 	base = res2mmio(res, 0, 0);
 	printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
 
-	if (RCBA32(0x2030) & (1 << 31)) {
+	if (RCBA32(CIR31) & (1 << 31)) {
 		reg32 = pci_read_config32(dev, 0x120);
 		reg32 &= 0xf8ffff01;
 		reg32 |= (1 << 24); // 2 << 24 for server
-		reg32 |= RCBA32(0x2030) & 0xfe;
+		reg32 |= RCBA32(CIR31) & 0xfe;
 		pci_write_config32(dev, 0x120, reg32);
 
 		reg16 = pci_read_config16(dev, 0x78);
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index c1631f4229..73fce3bf9f 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -72,24 +72,24 @@ write_iobp(u32 address, u32 val)
 void early_pch_init_native_dmi_pre(void)
 {
 	/* Link Capabilities Register */
-	RCBA32(0x21a4) = (RCBA32(0x21a4) & ~0x3fc00) |
+	RCBA32(LCAP) = (RCBA32(LCAP) & ~0x3fc00) |
 			 (3 << 10) | // L0s and L1 entry supported
 			 (2 << 12) | // L0s 128 ns to less than 256 ns
 			 (2 << 15);  // L1 2 us to less than 4 us
 
 	RCBA32(0x2340) = (RCBA32(0x2340) & ~0xff0000) | (0x3a << 16);
-	RCBA8(0x21b0) = (RCBA8(0x21b0) & ~0xf) | 2;
+	RCBA8(DLCTL2) = (RCBA8(DLCTL2) & ~0xf) | 2;
 }
 
 void early_pch_init_native_dmi_post(void)
 {
-	RCBA32(0x0050);	// !!! = 0x01200654
-	RCBA32(0x0050) = 0x01200654;
-	RCBA32(0x0050);	// !!! = 0x01200654
-	RCBA32(0x0050) = 0x012a0654;
-	RCBA32(0x0050);	// !!! = 0x012a0654
-	RCBA8(0x1114);	// !!! = 0x00
-	RCBA8(0x1114) = 0x05;
+	RCBA32(CIR0);	// !!! = 0x01200654
+	RCBA32(CIR0) = 0x01200654;
+	RCBA32(CIR0);	// !!! = 0x01200654
+	RCBA32(CIR0) = 0x012a0654;
+	RCBA32(CIR0);	// !!! = 0x012a0654
+	RCBA8(UPDCR);	// !!! = 0x00
+	RCBA8(UPDCR) = 0x05;
 
 	/*
 	 * Virtual Channel resources must match settings in DMIBAR!
@@ -106,42 +106,42 @@ void early_pch_init_native_dmi_post(void)
 	 * Map TC0 and TC3 and TC4 to VC0.
 	 */
 
-	RCBA32(0x2014) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1;
+	RCBA32(V0CTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1;
 
 	/* Virtual Channel 1 Resource Control Register.
 	 * Enable channel.
 	 * Set Virtual Channel Identifier.
 	 * Map TC1 and TC5 to VC1.
 	 */
-	RCBA32(0x2020) = (1 << 31) | (1 << 24) | (0x11 << 1);
+	RCBA32(V1CTL) = (1 << 31) | (1 << 24) | (0x11 << 1);
 	/* Read back register */
-	RCBA32(0x2020);
+	RCBA32(V1CTL);
 
 	/* Virtual Channel private Resource Control Register.
 	 * Enable channel.
 	 * Set Virtual Channel Identifier.
 	 * Map TC2 and TC6 to VCp.
 	 */
-	RCBA32(0x2030) = (1 << 31) | (2 << 24) | (0x22 << 1);
+	RCBA32(CIR31) = (1 << 31) | (2 << 24) | (0x22 << 1);
 	/* Read back register */
-	RCBA32(0x2030);
+	RCBA32(CIR31);
 
 	/* Virtual Channel ME Resource Control Register.
 	 * Enable channel.
 	 * Set Virtual Channel Identifier.
 	 * Map TC7 to VCm.
 	 */
-	RCBA32(0x2040) = (1 << 31) | (7 << 24) | (0x40 << 1);
+	RCBA32(CIR32) = (1 << 31) | (7 << 24) | (0x40 << 1);
 
 	/* Lock Virtual Channel Resource control register. */
-	RCBA32(0x0050) |= 0x80000000;
+	RCBA32(CIR0) |= TCLOCKDN;
 	/* Read back register */
-	RCBA32(0x0050);
+	RCBA32(CIR0);
 
 	/* Wait for virtual channels negotiation pending */
-	while (RCBA16(0x201a) & VCNEGPND)
+	while (RCBA16(V0STS) & VCNEGPND)
 		;
-	while (RCBA16(0x2026) & VCNEGPND)
+	while (RCBA16(V1STS) & VCNEGPND)
 		;
 	while (RCBA16(0x2036) & VCNEGPND)
 		;
@@ -155,17 +155,17 @@ early_pch_init_native (void)
 	pci_write_config8 (SOUTHBRIDGE, 0xa6,
 			    pci_read_config8 (SOUTHBRIDGE, 0xa6) | 2);
 
-	RCBA32(0x2088) = 0x00109000;
-	RCBA32(0x20ac); // !!! = 0x00000000
-	RCBA32(0x20ac) = 0x40000000;
+	RCBA32(CIR1) = 0x00109000;
+	RCBA32(REC); // !!! = 0x00000000
+	RCBA32(REC) = 0x40000000;
 	RCBA32(0x100c) = 0x01110000;
 	RCBA8(0x2340) = 0x1b;
-	RCBA32(0x2314); // !!! = 0x0a080000
-	RCBA32(0x2314) = 0x0a280000;
+	RCBA32(CIR6); // !!! = 0x0a080000
+	RCBA32(CIR6) = 0x0a280000;
 	RCBA32(0x2310); // !!! = 0xc809605b
 	RCBA32(0x2310) = 0xa809605b;
-	RCBA32(0x2324) = 0x00854c74;
-	RCBA8(0x0400);  // !!! = 0x00
+	RCBA32(DMC2) = 0x00854c74;
+	RCBA8(RPC);  // !!! = 0x00
 	RCBA32(0x2310); // !!! = 0xa809605b
 	RCBA32(0x2310) = 0xa809605b;
 	RCBA32(0x2310); // !!! = 0xa809605b
diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c
index e5d5625cab..e735e21656 100644
--- a/src/southbridge/intel/bd82x6x/early_usb.c
+++ b/src/southbridge/intel/bd82x6x/early_usb.c
@@ -39,7 +39,7 @@ void early_usb_init(const struct southbridge_usb_port *portmap)
 	write_pmbase16(UPRWC, read_pmbase16(UPRWC) | UPRWC_WR_EN);
 
 	for (i = 0; i < 14; i++)
-		RCBA32(0x3500 + 4 * i) = currents[portmap[i].current];
+		RCBA32(USBIR0 + 4 * i) = currents[portmap[i].current];
 	for (i = 0; i < 10; i++)
 		RCBA32(0x3538 + 4 * i) = 0;
 
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 661c1d483d..8794602978 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -269,9 +269,9 @@ static void pch_power_options(struct device *dev)
 	outl(reg32, pmbase + 0x04);
 
 	/* Clear magic status bits to prevent unexpected wake */
-	reg32 = RCBA32(0x3310);
+	reg32 = RCBA32(PRSTS);
 	reg32 |= (1 << 4)|(1 << 5)|(1 << 0);
-	RCBA32(0x3310) = reg32;
+	RCBA32(PRSTS) = reg32;
 
 	reg32 = RCBA32(0x3f02);
 	reg32 &= ~0xf;
@@ -283,40 +283,40 @@ static void cpt_pm_init(struct device *dev)
 {
 	printk(BIOS_DEBUG, "CougarPoint PM init\n");
 	pci_write_config8(dev, 0xa9, 0x47);
-	RCBA32_AND_OR(0x2238, ~0UL, (1 << 6)|(1 << 0));
-	RCBA32_AND_OR(0x228c, ~0UL, (1 << 0));
-	RCBA16_AND_OR(0x1100, ~0UL, (1 << 13)|(1 << 14));
-	RCBA16_AND_OR(0x0900, ~0UL, (1 << 14));
-	RCBA32(0x2304) = 0xc0388400;
-	RCBA32_AND_OR(0x2314, ~0UL, (1 << 5)|(1 << 18));
-	RCBA32_AND_OR(0x2320, ~0UL, (1 << 15)|(1 << 1));
-	RCBA32_AND_OR(0x3314, ~0x1f, 0xf);
-	RCBA32(0x3318) = 0x050f0000;
-	RCBA32(0x3324) = 0x04000000;
-	RCBA32_AND_OR(0x3340, ~0UL, 0xfffff);
-	RCBA32_AND_OR(0x3344, ~0UL, (1 << 1));
-	RCBA32(0x3360) = 0x0001c000;
-	RCBA32(0x3368) = 0x00061100;
-	RCBA32(0x3378) = 0x7f8fdfff;
-	RCBA32(0x337c) = 0x000003fc;
-	RCBA32(0x3388) = 0x00001000;
-	RCBA32(0x3390) = 0x0001c000;
-	RCBA32(0x33a0) = 0x00000800;
-	RCBA32(0x33b0) = 0x00001000;
-	RCBA32(0x33c0) = 0x00093900;
-	RCBA32(0x33cc) = 0x24653002;
-	RCBA32(0x33d0) = 0x062108fe;
-	RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060);
-	RCBA32(0x3a28) = 0x01010000;
-	RCBA32(0x3a2c) = 0x01010404;
-	RCBA32(0x3a80) = 0x01041041;
-	RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001);
-	RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */
-	RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0));  /* SATA 4/5 disabled */
-	RCBA32(0x3a6c) = 0x00000001;
+	RCBA32_AND_OR(CIR30, ~0UL, (1 << 6)|(1 << 0));
+	RCBA32_AND_OR(CIR5, ~0UL, (1 << 0));
+	RCBA16_AND_OR(CIR3, ~0UL, (1 << 13)|(1 << 14));
+	RCBA16_AND_OR(CIR2, ~0UL, (1 << 14));
+	RCBA32(DMC) = 0xc0388400;
+	RCBA32_AND_OR(CIR6, ~0UL, (1 << 5)|(1 << 18));
+	RCBA32_AND_OR(CIR9, ~0UL, (1 << 15)|(1 << 1));
+	RCBA32_AND_OR(CIR7, ~0x1f, 0xf);
+	RCBA32(PM_CFG) = 0x050f0000;
+	RCBA32(CIR8) = 0x04000000;
+	RCBA32_AND_OR(CIR10, ~0UL, 0xfffff);
+	RCBA32_AND_OR(CIR11, ~0UL, (1 << 1));
+	RCBA32(CIR12) = 0x0001c000;
+	RCBA32(CIR14) = 0x00061100;
+	RCBA32(CIR15) = 0x7f8fdfff;
+	RCBA32(CIR13) = 0x000003fc;
+	RCBA32(CIR16) = 0x00001000;
+	RCBA32(CIR18) = 0x0001c000;
+	RCBA32(CIR17) = 0x00000800;
+	RCBA32(CIR23) = 0x00001000;
+	RCBA32(CIR19) = 0x00093900;
+	RCBA32(CIR20) = 0x24653002;
+	RCBA32(CIR21) = 0x062108fe;
+	RCBA32_AND_OR(CIR22, 0xf000f000, 0x00670060);
+	RCBA32(CIR24) = 0x01010000;
+	RCBA32(CIR25) = 0x01010404;
+	RCBA32(CIR27) = 0x01041041;
+	RCBA32_AND_OR(CIR28, ~0x0000ffff, 0x00001001);
+	RCBA32_AND_OR(CIR28, ~0UL, (1 << 24)); /* SATA 2/3 disabled */
+	RCBA32_AND_OR(CIR29, ~0UL, (1 << 0));  /* SATA 4/5 disabled */
+	RCBA32(CIR26) = 0x00000001;
 	RCBA32_AND_OR(0x2344, 0x00ffff00, 0xff00000c);
 	RCBA32_AND_OR(0x80c, ~(0xff << 20), 0x11 << 20);
-	RCBA32(0x33c8) = 0;
+	RCBA32(PMSYNC_CFG) = 0;
 	RCBA32_AND_OR(0x21b0, ~0UL, 0xf);
 }
 
@@ -325,41 +325,41 @@ static void ppt_pm_init(struct device *dev)
 {
 	printk(BIOS_DEBUG, "PantherPoint PM init\n");
 	pci_write_config8(dev, 0xa9, 0x47);
-	RCBA32_AND_OR(0x2238, ~0UL, (1 << 0));
-	RCBA32_AND_OR(0x228c, ~0UL, (1 << 0));
-	RCBA16_AND_OR(0x1100, ~0UL, (1 << 13)|(1 << 14));
-	RCBA16_AND_OR(0x0900, ~0UL, (1 << 14));
-	RCBA32(0x2304) = 0xc03b8400;
-	RCBA32_AND_OR(0x2314, ~0UL, (1 << 5)|(1 << 18));
-	RCBA32_AND_OR(0x2320, ~0UL, (1 << 15)|(1 << 1));
-	RCBA32_AND_OR(0x3314, ~0x1f, 0xf);
-	RCBA32(0x3318) = 0x054f0000;
-	RCBA32(0x3324) = 0x04000000;
-	RCBA32_AND_OR(0x3340, ~0UL, 0xfffff);
-	RCBA32_AND_OR(0x3344, ~0UL, (1 << 1)|(1 << 0));
-	RCBA32(0x3360) = 0x0001c000;
-	RCBA32(0x3368) = 0x00061100;
-	RCBA32(0x3378) = 0x7f8fdfff;
-	RCBA32(0x337c) = 0x000003fd;
-	RCBA32(0x3388) = 0x00001000;
-	RCBA32(0x3390) = 0x0001c000;
-	RCBA32(0x33a0) = 0x00000800;
-	RCBA32(0x33b0) = 0x00001000;
-	RCBA32(0x33c0) = 0x00093900;
-	RCBA32(0x33cc) = 0x24653002;
-	RCBA32(0x33d0) = 0x067388fe;
-	RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060);
-	RCBA32(0x3a28) = 0x01010000;
-	RCBA32(0x3a2c) = 0x01010404;
-	RCBA32(0x3a80) = 0x01040000;
-	RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001);
-	RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */
-	RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0));  /* SATA 4/5 disabled */
-	RCBA32(0x3a6c) = 0x00000001;
+	RCBA32_AND_OR(CIR30, ~0UL, (1 << 0));
+	RCBA32_AND_OR(CIR5, ~0UL, (1 << 0));
+	RCBA16_AND_OR(CIR3, ~0UL, (1 << 13)|(1 << 14));
+	RCBA16_AND_OR(CIR2, ~0UL, (1 << 14));
+	RCBA32(DMC) = 0xc03b8400;
+	RCBA32_AND_OR(CIR6, ~0UL, (1 << 5)|(1 << 18));
+	RCBA32_AND_OR(CIR9, ~0UL, (1 << 15)|(1 << 1));
+	RCBA32_AND_OR(CIR7, ~0x1f, 0xf);
+	RCBA32(PM_CFG) = 0x054f0000;
+	RCBA32(CIR8) = 0x04000000;
+	RCBA32_AND_OR(CIR10, ~0UL, 0xfffff);
+	RCBA32_AND_OR(CIR11, ~0UL, (1 << 1)|(1 << 0));
+	RCBA32(CIR12) = 0x0001c000;
+	RCBA32(CIR14) = 0x00061100;
+	RCBA32(CIR15) = 0x7f8fdfff;
+	RCBA32(CIR13) = 0x000003fd;
+	RCBA32(CIR16) = 0x00001000;
+	RCBA32(CIR18) = 0x0001c000;
+	RCBA32(CIR17) = 0x00000800;
+	RCBA32(CIR23) = 0x00001000;
+	RCBA32(CIR19) = 0x00093900;
+	RCBA32(CIR20) = 0x24653002;
+	RCBA32(CIR21) = 0x067388fe;
+	RCBA32_AND_OR(CIR22, 0xf000f000, 0x00670060);
+	RCBA32(CIR24) = 0x01010000;
+	RCBA32(CIR25) = 0x01010404;
+	RCBA32(CIR27) = 0x01040000;
+	RCBA32_AND_OR(CIR28, ~0x0000ffff, 0x00001001);
+	RCBA32_AND_OR(CIR28, ~0UL, (1 << 24)); /* SATA 2/3 disabled */
+	RCBA32_AND_OR(CIR29, ~0UL, (1 << 0));  /* SATA 4/5 disabled */
+	RCBA32(CIR26) = 0x00000001;
 	RCBA32_AND_OR(0x2344, 0x00ffff00, 0xff00000c);
 	RCBA32_AND_OR(0x80c, ~(0xff << 20), 0x11 << 20);
 	RCBA32_AND_OR(0x33a4, ~0UL, (1 << 0));
-	RCBA32(0x33c8) = 0;
+	RCBA32(PMSYNC_CFG) = 0;
 	RCBA32_AND_OR(0x21b0, ~0UL, 0xf);
 }
 
@@ -385,7 +385,7 @@ static void enable_clock_gating(struct device *dev)
 	u32 reg32;
 	u16 reg16;
 
-	RCBA32_AND_OR(0x2234, ~0UL, 0xf);
+	RCBA32_AND_OR(DMIC, ~0UL, 0xf);
 
 	reg16 = pci_read_config16(dev, GEN_PMCON_1);
 	reg16 |= (1 << 2) | (1 << 11);
@@ -453,9 +453,9 @@ static void pch_fixups(struct device *dev)
 	/*
 	 * Enable DMI ASPM in the PCH
 	 */
-	RCBA32_AND_OR(0x2304, ~(1 << 10), 0);
-	RCBA32_OR(0x21a4, (1 << 11)|(1 << 10));
-	RCBA32_OR(0x21a8, 0x3);
+	RCBA32_AND_OR(DMC, ~(1 << 10), 0);
+	RCBA32_OR(LCAP, (1 << 11)|(1 << 10));
+	RCBA32_OR(LCTL, 0x3);
 }
 
 static void pch_decode_init(struct device *dev)
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 4369b5c162..bc6c8b333f 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -256,19 +256,8 @@ early_usb_init (const struct southbridge_usb_port *portmap);
 
 #define PMBASE		0x40
 
-#define VCH		0x0000	/* 32bit */
-#define VCAP1		0x0004	/* 32bit */
-#define VCAP2		0x0008	/* 32bit */
-#define PVC		0x000c	/* 16bit */
-#define PVS		0x000e	/* 16bit */
-
-#define V0CAP		0x0010	/* 32bit */
-#define V0CTL		0x0014	/* 32bit */
-#define V0STS		0x001a	/* 16bit */
-
-#define V1CAP		0x001c	/* 32bit */
-#define V1CTL		0x0020	/* 32bit */
-#define V1STS		0x0026	/* 16bit */
+#define CIR0		0x0050	/* 32bit */
+#define  TCLOCKDN	(1u << 31)
 
 #define RCTCL		0x0100	/* 32bit */
 #define ESD		0x0104	/* 32bit */
@@ -293,6 +282,10 @@ early_usb_init (const struct southbridge_usb_port *portmap);
 #define RPC		0x0400	/* 32bit */
 #define RPFN		0x0404	/* 32bit */
 
+#define CIR2		0x900	/* 16bit */
+#define CIR3		0x1100	/* 16bit */
+#define UPDCR		0x1114	/* 32bit */
+
 /* Root Port configuratinon space hide */
 #define RPFN_HIDE(port)         (1 << (((port) * 4) + 3))
 /* Get the function number assigned to a Root Port */
@@ -335,6 +328,27 @@ early_usb_init (const struct southbridge_usb_port *portmap);
 #define PIRQG		6
 #define PIRQH		7
 
+/* DMI control */
+#define V0CTL		0x2014	/* 32bit */
+#define V0STS		0x201a	/* 16bit */
+#define V1CTL		0x2020	/* 32bit */
+#define V1STS		0x2026	/* 16bit */
+#define CIR31		0x2030	/* 32bit */
+#define CIR32		0x2040	/* 32bit */
+#define CIR1		0x2088	/* 32bit */
+#define REC		0x20ac	/* 32bit */
+#define LCAP		0x21a4	/* 32bit */
+#define LCTL		0x21a8	/* 16bit */
+#define LSTS		0x21aa	/* 16bit */
+#define DLCTL2		0x21b0	/* 16bit */
+#define DMIC		0x2234	/* 32bit */
+#define CIR30		0x2238	/* 32bit */
+#define CIR5		0x228c	/* 32bit */
+#define DMC		0x2304	/* 32bit */
+#define CIR6		0x2314	/* 32bit */
+#define CIR9		0x2320	/* 32bit */
+#define DMC2		0x2324	/* 32bit - name guessed */
+
 /* IO Buffer Programming */
 #define IOBPIRI		0x2330
 #define IOBPD		0x2334
@@ -391,6 +405,26 @@ early_usb_init (const struct southbridge_usb_port *portmap);
   RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
                ((b) << DIR_IBR) | ((a) << DIR_IAR))
 
+#define PRSTS		0x3310	/* 32bit */
+#define CIR7		0x3314	/* 32bit */
+#define PM_CFG		0x3318	/* 32bit */
+#define CIR8		0x3324	/* 32bit */
+#define CIR10		0x3340	/* 32bit */
+#define CIR11		0x3344	/* 32bit */
+#define CIR12		0x3360	/* 32bit */
+#define CIR14		0x3368	/* 32bit */
+#define CIR15		0x3378	/* 32bit */
+#define CIR13		0x337c	/* 32bit */
+#define CIR16		0x3388	/* 32bit */
+#define CIR18		0x3390	/* 32bit */
+#define CIR17		0x33a0	/* 32bit */
+#define CIR23		0x33b0	/* 32bit */
+#define CIR19		0x33c0	/* 32bit */
+#define PMSYNC_CFG	0x33c8	/* 32bit */
+#define CIR20		0x33cc	/* 32bit */
+#define CIR21		0x33d0	/* 32bit */
+#define CIR22		0x33d4	/* 32bit */
+
 #define RC		0x3400	/* 32bit */
 #define HPTC		0x3404	/* 32bit */
 #define GCS		0x3410	/* 32bit */
@@ -422,11 +456,38 @@ early_usb_init (const struct southbridge_usb_port *portmap);
 #define PCH_DISABLE_MEI1	(1 << 1)
 #define PCH_ENABLE_DBDF		(1 << 0)
 
+/* USB Initialization Registers[13:0] */
+#define USBIR0		0x3500	/* 32bit */
+#define USBIR1		0x3504	/* 32bit */
+#define USBIR2		0x3508	/* 32bit */
+#define USBIR3		0x350c	/* 32bit */
+#define USBIR4		0x3510	/* 32bit */
+#define USBIR5		0x3514	/* 32bit */
+#define USBIR6		0x3518	/* 32bit */
+#define USBIR7		0x351c	/* 32bit */
+#define USBIR8		0x3520	/* 32bit */
+#define USBIR9		0x3524	/* 32bit */
+#define USBIR10		0x3528	/* 32bit */
+#define USBIR11		0x352c	/* 32bit */
+#define USBIR12		0x3530	/* 32bit */
+#define USBIR13		0x3534	/* 32bit */
+
+/* Miscellaneous Control Register */
+#define MISCCTL		0x3590	/* 32bit */
 /* USB Port Disable Override */
 #define USBPDO		0x359c	/* 32bit */
 /* USB Overcurrent MAP Register */
 #define USBOCM1		0x35a0	/* 32bit */
 #define USBOCM2		0x35a4	/* 32bit */
+/* Rate Matching Hub Wake Control Register */
+#define RMHWKCTL	0x35b0	/* 32bit */
+
+#define CIR24		0x3a28	/* 32bit */
+#define CIR25		0x3a2c	/* 32bit */
+#define CIR26		0x3a6c	/* 32bit */
+#define CIR27		0x3a80	/* 32bit */
+#define CIR28		0x3a84	/* 32bit */
+#define CIR29		0x3a88	/* 32bit */
 
 /* XHCI USB 3.0 */
 #define XOCM		0xc0	/* 32bit */
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index 0bc75b54a5..97306e44cb 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -114,7 +114,7 @@ static void pch_pcie_pm_early(struct device *dev)
 	/* Adjust ASPM L1 exit latency */
 	reg32 = pci_read_config32(dev, 0x4c);
 	reg32 &= ~((1 << 17) | (1 << 16) | (1 << 15));
-	if (RCBA32(0x2320) & (1 << 16)) {
+	if (RCBA32(CIR9) & (1 << 16)) {
 		/* If RCBA+2320[15]=1 set ASPM L1 to 8-16us */
 		reg32 |= (1 << 17);
 	} else {
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index 8fe3e41d6d..2c2f9d97e9 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -28,9 +28,9 @@ static void usb_ehci_init(struct device *dev)
 	u32 reg32;
 
 	/* Disable Wake on Disconnect in RMH */
-	reg32 = RCBA32(0x35b0);
+	reg32 = RCBA32(RMHWKCTL);
 	reg32 |= 0x22;
-	RCBA32(0x35b0) = reg32;
+	RCBA32(RMHWKCTL) = reg32;
 
 	printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");