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| author | Myles Watson <mylesgw@gmail.com> | 2010-04-27 15:00:18 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2010-04-27 15:00:18 +0000 |
| commit | 636d9244259a86afd5af64268c5f6ab660d522fa (patch) | |
| tree | ed3f3eae6b506f810f16bc5693cf1df35b712ac3 /src/southbridge/intel | |
| parent | 9ebd65d77f85233983eebcb6ed9e2cde8af2a5f1 (diff) | |
| download | coreboot-636d9244259a86afd5af64268c5f6ab660d522fa.tar.xz | |
Enable the cache before initializing the processor name, like model_10 does.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5511 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel')
0 files changed, 0 insertions, 0 deletions