intel/spi: Switch to native PCI config accessors

Change-Id: If7190ac105b2a65a9576709955c3cc840b95dcdf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

2 files changed, 8 insertions, 65 deletions

diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 60c0b8dd6e..1d871d2c5d 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -24,6 +24,7 @@
 #include <delay.h>
 #include <arch/io.h>
 #include <console/console.h>
+#include <device/device.h>
 #include <device/pci.h>
 #include <spi_flash.h>
 
@@ -34,36 +35,6 @@
 #define HSFC_FDBC_OFF		8	/* 8-13: Flash Data Byte Count */
 #define HSFC_FDBC		(0x3f << HSFC_FDBC_OFF)
 
-
-#ifdef __SMM__
-#define pci_read_config_byte(dev, reg, targ)\
-	*(targ) = pci_read_config8(dev, reg)
-#define pci_read_config_word(dev, reg, targ)\
-	*(targ) = pci_read_config16(dev, reg)
-#define pci_read_config_dword(dev, reg, targ)\
-	*(targ) = pci_read_config32(dev, reg)
-#define pci_write_config_byte(dev, reg, val)\
-	pci_write_config8(dev, reg, val)
-#define pci_write_config_word(dev, reg, val)\
-	pci_write_config16(dev, reg, val)
-#define pci_write_config_dword(dev, reg, val)\
-	pci_write_config32(dev, reg, val)
-#else /* !__SMM__ */
-#include <device/device.h>
-#define pci_read_config_byte(dev, reg, targ)\
-	*(targ) = pci_read_config8(dev, reg)
-#define pci_read_config_word(dev, reg, targ)\
-	*(targ) = pci_read_config16(dev, reg)
-#define pci_read_config_dword(dev, reg, targ)\
-	*(targ) = pci_read_config32(dev, reg)
-#define pci_write_config_byte(dev, reg, val)\
-	pci_write_config8(dev, reg, val)
-#define pci_write_config_word(dev, reg, val)\
-	pci_write_config16(dev, reg, val)
-#define pci_write_config_dword(dev, reg, val)\
-	pci_write_config32(dev, reg, val)
-#endif /* !__SMM__ */
-
 static int spi_is_multichip(void);
 
 typedef struct spi_slave ich_spi_slave;
@@ -308,7 +279,7 @@ void spi_init(void)
 	struct device *dev = pcidev_on_root(31, 0);
 #endif
 
-	pci_read_config_dword(dev, 0xf0, &rcba);
+	rcba = pci_read_config32(dev, 0xf0);
 	/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
 	rcrb = (uint8_t *)(rcba & 0xffffc000);
 	if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) {
@@ -356,10 +327,10 @@ void spi_init(void)
 	ich_set_bbar(0);
 
 	/* Disable the BIOS write protect so write commands are allowed. */
-	pci_read_config_byte(dev, 0xdc, &bios_cntl);
+	bios_cntl = pci_read_config8(dev, 0xdc);
 	/* Deassert SMM BIOS Write Protect Disable. */
 	bios_cntl &= ~(1 << 5);
-	pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1);
+	pci_write_config8(dev, 0xdc, bios_cntl | 0x1);
 }
 
 static void spi_init_cb(void *unused)
diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c
index e10072a46c..227422b270 100644
--- a/src/southbridge/intel/fsp_rangeley/spi.c
+++ b/src/southbridge/intel/fsp_rangeley/spi.c
@@ -21,6 +21,8 @@
 #include <delay.h>
 #include <arch/io.h>
 #include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
 #include <device/pci_ids.h>
 
 #include <spi_flash.h>
@@ -28,36 +30,6 @@
 
 static int ich_status_poll(u16 bitmask, int wait_til_set);
 
-#ifdef __SMM__
-#define pci_read_config_byte(dev, reg, targ)\
-	*(targ) = pci_read_config8(dev, reg)
-#define pci_read_config_word(dev, reg, targ)\
-	*(targ) = pci_read_config16(dev, reg)
-#define pci_read_config_dword(dev, reg, targ)\
-	*(targ) = pci_read_config32(dev, reg)
-#define pci_write_config_byte(dev, reg, val)\
-	pci_write_config8(dev, reg, val)
-#define pci_write_config_word(dev, reg, val)\
-	pci_write_config16(dev, reg, val)
-#define pci_write_config_dword(dev, reg, val)\
-	pci_write_config32(dev, reg, val)
-#else /* !__SMM__ */
-#include <device/device.h>
-#include <device/pci.h>
-#define pci_read_config_byte(dev, reg, targ)\
-	*(targ) = pci_read_config8(dev, reg)
-#define pci_read_config_word(dev, reg, targ)\
-	*(targ) = pci_read_config16(dev, reg)
-#define pci_read_config_dword(dev, reg, targ)\
-	*(targ) = pci_read_config32(dev, reg)
-#define pci_write_config_byte(dev, reg, val)\
-	pci_write_config8(dev, reg, val)
-#define pci_write_config_word(dev, reg, val)\
-	pci_write_config16(dev, reg, val)
-#define pci_write_config_dword(dev, reg, val)\
-	pci_write_config32(dev, reg, val)
-#endif /* !__SMM__ */
-
 typedef struct spi_slave ich_spi_slave;
 
 static int ichspi_lock = 0;
@@ -349,7 +321,7 @@ void spi_init(void)
 #else
 	struct device *dev = pcidev_on_root(31, 0);
 #endif
-	pci_read_config_dword(dev, 0, &ids);
+	ids = pci_read_config32(dev, 0);
 	vendor_id = ids;
 	device_id = (ids >> 16);
 
@@ -370,7 +342,7 @@ void spi_init(void)
 		{
 			uint8_t *spibase; /* SPI Base Address */
 			uint32_t sbase; /* SPI Base Address Register */
-			pci_read_config_dword(dev, 0x54, &sbase);
+			sbase = pci_read_config32(dev, 0x54);
 			/* Bits 31-9 are the base address, 8-4 are reserved, 3-0 are used. */
 			spibase = (uint8_t *)(sbase & 0xffffff00);
 			ich10_spi_regs *ich10_spi =