intel/bd82x6x: Use generated ACPI PIRQ

Enable change Ic6b8ce4a9db50211a9c26221ca10105c5a0829a0
(sb/intel/common: Automatically generate ACPI PIRQ) for BD82X6X.

This generates the main ACPI _PRT table automatically based on the
chipset registers.

Tested on Intel NUC DCP847SKE with Linux 4.13.14:
$ cat /proc/interrupts
           CPU0       CPU1
  0:         23          0   IO-APIC   2-edge      timer
  8:          1          0   IO-APIC   8-edge      rtc0
  9:          0          0   IO-APIC   9-fasteoi   acpi
 19:         86          0   IO-APIC  19-fasteoi   ehci_hcd:usb1
 23:          0          0   IO-APIC  23-fasteoi   i801_smbus
[...MSI and other interrupts skipped...]

Log messages:
ACPI_PIRQ_GEN PCI: 00:02.0: pin=1 pirq=1
ACPI_PIRQ_GEN PCI: 00:1b.0: pin=1 pirq=1
ACPI_PIRQ_GEN PCI: 00:1c.0: pin=1 pirq=2
ACPI_PIRQ_GEN PCI: 00:1c.1: pin=2 pirq=6
ACPI_PIRQ_GEN PCI: 00:1c.2: pin=3 pirq=4
ACPI_PIRQ_GEN PCI: 00:1d.0: pin=1 pirq=4
ACPI_PIRQ_GEN PCI: 00:1f.2: pin=1 pirq=2
ACPI_PIRQ_GEN PCI: 00:1f.3: pin=2 pirq=8
ACPI_PIRQ_GEN PCI: 00:04.0: pin=1 pirq=1

Generated _PRT:
    Scope (\_SB.PCI0)
    {
        Method (_PRT, 0, NotSerialized)  // _PRT: PCI Routing Table
        {
            If (PICM)
            {
                Return (Package (0x09)
                {
                    Package (0x04)
                    {
                        0x0002FFFF,
                        0x00000000,
                        0x00000000,
                        0x00000010
                    },

                    Package (0x04)
                    {
                        0x001BFFFF,
                        0x00000000,
                        0x00000000,
                        0x00000010
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000000,
                        0x00000000,
                        0x00000011
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000001,
                        0x00000000,
                        0x00000015
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000002,
                        0x00000000,
                        0x00000013
                    },

                    Package (0x04)
                    {
                        0x001DFFFF,
                        0x00000000,
                        0x00000000,
                        0x00000013
                    },

                    Package (0x04)
                    {
                        0x001FFFFF,
                        0x00000000,
                        0x00000000,
                        0x00000011
                    },

                    Package (0x04)
                    {
                        0x001FFFFF,
                        0x00000001,
                        0x00000000,
                        0x00000017
                    },

                    Package (0x04)
                    {
                        0x0004FFFF,
                        0x00000000,
                        0x00000000,
                        0x00000010
                    }
                })
            }
            Else
            {
                Return (Package (0x09)
                {
                    Package (0x04)
                    {
                        0x0002FFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKA,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001BFFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKA,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKB,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000001,
                        \_SB.PCI0.LPCB.LNKF,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001CFFFF,
                        0x00000002,
                        \_SB.PCI0.LPCB.LNKD,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001DFFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKD,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001FFFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKB,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x001FFFFF,
                        0x00000001,
                        \_SB.PCI0.LPCB.LNKH,
                        0x00000000
                    },

                    Package (0x04)
                    {
                        0x0004FFFF,
                        0x00000000,
                        \_SB.PCI0.LPCB.LNKA,
                        0x00000000
                    }
                })
            }
        }
    }

Change-Id: I832a86925283d61b64b8268246d9e6f11994c120
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/22859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

3 files changed, 3 insertions, 77 deletions

diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index fe1ca3480b..ed2b9794c6 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -25,6 +25,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	def_bool y
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select SOUTHBRIDGE_INTEL_COMMON
+	select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
 	select SOUTHBRIDGE_INTEL_COMMON_SPI
 	select IOAPIC
diff --git a/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl b/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl
deleted file mode 100644
index 0e6f9605e2..0000000000
--- a/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* PCI Interrupt Routing */
-Method(_PRT)
-{
-	If (PICM) {
-		Return (Package() {
-			/* Onboard graphics (IGD)	0:2.0 */
-			Package() { 0x0002ffff, 0, 0, 16 },/*  GFX                INTA -> PIRQA (MSI) */
-			/* PCI Express Graphics (PEG)	0:1.0 */
-			Package() { 0x0001ffff, 0, 0, 16 },/*  GFX         PCIe   INTA -> PIRQA (MSI) */
-			Package() { 0x0001ffff, 0, 0, 17 },/*  GFX         PCIe   INTB -> PIRQB (MSI) */
-			Package() { 0x0001ffff, 0, 0, 18 },/*  GFX         PCIe   INTC -> PIRQC (MSI) */
-			Package() { 0x0001ffff, 0, 0, 19 },/*  GFX         PCIe   INTD -> PIRQD (MSI) */
-			/* XHCI	0:14.0 (ivy only) */
-			Package() { 0x0014ffff, 0, 0, 19 },
-			/* High Definition Audio	0:1b.0 */
-			Package() { 0x001bffff, 0, 0, 16 },/*  D27IP_ZIP   HDA    INTA -> PIRQA (MSI) */
-			/* PCIe Root Ports		0:1c.x */
-			Package() { 0x001cffff, 0, 0, 17 },/*  D28IP_P1IP  PCIe   INTA -> PIRQB */
-			Package() { 0x001cffff, 1, 0, 21 },/*  D28IP_P2IP  PCIe   INTB -> PIRQF */
-			Package() { 0x001cffff, 2, 0, 19 },/*  D28IP_P3IP  PCIe   INTC -> PIRQD */
-			Package() { 0x001cffff, 3, 0, 20 },/*  D28IP_P3IP  PCIe   INTD -> PIRQE */
-			/* EHCI	#1			0:1d.0 */
-			Package() { 0x001dffff, 0, 0, 19 },/*  D29IP_E1P   EHCI1  INTA -> PIRQD */
-			/* EHCI	#2			0:1a.0 */
-			Package() { 0x001affff, 0, 0, 21 },/*  D26IP_E2P   EHCI2  INTA -> PIRQF */
-			/* LPC devices			0:1f.0 */
-			Package() { 0x001fffff, 0, 0, 17 }, /* D31IP_SIP   SATA   INTA -> PIRQB (MSI) */
-			Package() { 0x001fffff, 1, 0, 23 }, /* D31IP_SMIP  SMBUS  INTB -> PIRQH */
-			Package() { 0x001fffff, 2, 0, 16 }, /* D31IP_TTIP  THRT   INTC -> PIRQA */
-			Package() { 0x001fffff, 3, 0, 18 },
-		})
-	} Else {
-		Return (Package() {
-			/* Onboard graphics (IGD)	0:2.0 */
-			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			/* PCI Express Graphics (PEG)	0:1.0 */
-			Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
-			Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
-			Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
-			/* XHCI   0:14.0 (ivy only) */
-			Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
-			/* High Definition Audio	0:1b.0 */
-			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			/* PCIe Root Ports		0:1c.x */
-			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
-			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
-			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
-			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
-			/* EHCI	#1			0:1d.0 */
-			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
-			/* EHCI	#2			0:1a.0 */
-			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
-			/* LPC device			0:1f.0 */
-			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
-			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
-			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
-			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
-		})
-	}
-}
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 2bfc1e3374..7f61669cf9 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -35,6 +35,7 @@
 #include "pch.h"
 #include "nvs.h"
 #include <southbridge/intel/common/pciehp.h>
+#include <southbridge/intel/common/acpi_pirq_gen.h>
 
 #define NMI_OFF	0
 
@@ -821,6 +822,7 @@ static void southbridge_fill_ssdt(device_t device)
 	config_t *chip = dev->chip_info;
 
 	intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);
+	intel_acpi_gen_def_acpi_pirq(dev);
 }
 
 static void lpc_final(struct device *dev)