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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-03-01 11:07:06 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-04 13:58:11 +0000 |
| commit | 80505a6fef22587b5e5a4037d4e83c81236814fd (patch) | |
| tree | 1dfac08bc372a8713d2f52a022786e66032edc6d /src/southbridge/intel | |
| parent | 2796b242b20ca4276f64d09ddabc3ee4c5a81148 (diff) | |
| download | coreboot-80505a6fef22587b5e5a4037d4e83c81236814fd.tar.xz | |
sb/intel/i82801gx: Remove unnecessary/redundant ACPI offset operator
Using ACPICA version 20180927 or greater, IASL detects Unnecessary/redundant
uses of the Offset() operator within a Field Unit list.
It then sends a remark "^ Unnecessary/redundant use of Offset".
Offsets refer to the current offset are unnecessary.
example:
OperationRegion (OPR1, SystemMemory, 0x100, 0x100)
Field (OPR1)
{
Offset (0), // Never needed
FLD1, 32,
Offset (4), // Redundant, offset is already 4 (bytes)
FLD2, 8,
Offset (64), // OK use of Offset.
FLD3, 16,
}
We will have those remarks:
dsdt.asl 14: Offset (0),
Remark 2158 - ^ Unnecessary/redundant use of Offset
operator
dsdt.asl 16: Offset (4),
Remark 2158 - ^ Unnecessary/redundant use of Offset
operator
Change-Id: If53072c6a91dd794c70d1fab8697b1713d400fe8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/i82801gx/acpi/globalnvs.asl | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/acpi/ich7.asl | 14 |
2 files changed, 7 insertions, 11 deletions
diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index 33472b65ed..650b07c2a2 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -30,7 +30,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x100) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter @@ -48,7 +47,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) LINX, 8, // 0x12 - Linux OS DCKN, 8, // 0x13 - PCIe docking state /* Thermal policy */ - Offset (0x14), ACTT, 8, // 0x14 - active trip point TPSV, 8, // 0x15 - passive trip point TC1V, 8, // 0x16 - passive trip point TC1 @@ -87,7 +85,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) UTIL, 8, // 0x3a - ACIN, 8, // 0x3b - /* Integrated Graphics Device */ - Offset (0x3c), IGDS, 8, // 0x3c - IGD state (primary = 1) TLST, 8, // 0x3d - Display Toggle List pointer CADL, 8, // 0x3e - Currently Attached Devices List @@ -95,7 +92,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) CSTE, 16, // 0x40 - Current display state NSTE, 16, // 0x42 - Next display state SSTE, 16, // 0x44 - Set display state - Offset (0x46), NDID, 8, // 0x46 - Number of Device IDs DID1, 32, // 0x47 - Device ID 1 DID2, 32, // 0x4b - Device ID 2 diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl index 38ca4831b1..d24c8af135 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl @@ -43,12 +43,12 @@ Scope(\) OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c) Field(GPIO, ByteAcc, NoLock, Preserve) { - Offset(0x00), // GPIO Use Select + // GPIO Use Select GU00, 8, GU01, 8, GU02, 8, GU03, 8, - Offset(0x04), // GPIO IO Select + // GPIO IO Select GIO0, 8, GIO1, 8, GIO2, 8, @@ -96,17 +96,17 @@ Scope(\) GIV1, 8, GIV2, 8, GIV3, 8, - Offset(0x30), // GPIO Use Select 2 + // GPIO Use Select 2 GU04, 8, GU05, 8, GU06, 8, GU07, 8, - Offset(0x34), // GPIO IO Select 2 + // GPIO IO Select 2 GIO4, 8, GIO5, 8, GIO6, 8, GIO7, 8, - Offset(0x38), // GPIO Level 2 + // GPIO Level 2 GP32, 1, GP33, 1, GP34, 1, @@ -125,7 +125,7 @@ Scope(\) OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) Field(RCRB, DWordAcc, Lock, Preserve) { - Offset(0x0000), // Backbone + // Backbone Offset(0x1000), // Chipset Offset(0x3000), // Legacy Configuration Registers Offset(0x3404), // High Performance Timer Configuration @@ -148,7 +148,7 @@ Scope(\) , 2, // Reserved LPBD, 1, // LPC bridge disable EHCD, 1, // EHCI disable - Offset(0x341a), // FD Root Ports + // FD Root Ports RP1D, 1, // Root Port 1 disable RP2D, 1, // Root Port 2 disable RP3D, 1, // Root Port 3 disable |