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authorElyes HAOUAS <ehaouas@noos.fr>2019-05-09 13:24:14 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-05-10 15:15:28 +0000
commit9646cfe989a096372a717d8ef16ce5096d1b2708 (patch)
treeba822c74f89e875382bc9e7bb11b9cf3eaa42753 /src/southbridge/intel
parentc9f6bd90857d3a7efe08c60f7f5fc19995fb1756 (diff)
downloadcoreboot-9646cfe989a096372a717d8ef16ce5096d1b2708.tar.xz
sb/bd82x6x: Don't rewrite over BCTRL
PCI_MIN_GNT is defined at offset 0x3e in <pci_def.h> which does not apply to this PCI bridge because it is only defined for "Header type 0 (normal devices)" (line 82). Some lines obove that code line, the "write" on BCTRL is already done. Change-Id: I8f1b98ba627947ab6652a4ba31d2acb159dd3e32 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32700 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/bd82x6x/pci.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c
index c3b82577e1..2186287df2 100644
--- a/src/southbridge/intel/bd82x6x/pci.c
+++ b/src/southbridge/intel/bd82x6x/pci.c
@@ -47,9 +47,6 @@ static void pci_init(struct device *dev)
reg8 |= (0x04 << 3);
pci_write_config8(dev, SMLT, reg8);
- /* Will this improve throughput of bus masters? */
- pci_write_config8(dev, PCI_MIN_GNT, 0x06);
-
/* Clear errors in status registers */
reg16 = pci_read_config16(dev, PSTS);
//reg16 |= 0xf900;