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| author | Marc Jones <marc.jones@se-eng.com> | 2013-10-30 23:56:26 -0600 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2014-07-04 17:50:24 +0200 |
| commit | e05cba2c7225d43913fea3b0066f2e24990cee6f (patch) | |
| tree | 6cdea4dc9e3119342e36933a2ea92347c046b2c8 /src/southbridge/intel | |
| parent | 5a45b04ac0e4a296f1df1984200766151c66c42c (diff) | |
| download | coreboot-e05cba2c7225d43913fea3b0066f2e24990cee6f.tar.xz | |
intel/lynxpoint: Add SATA DEVSLP disable option
Add the chip option to disable SATA DEVSLP. This disables
the SDS bit in the SATA CAP2 register.
BUG=chrome-os-partner:23186
BRANCH=leon
TEST=Manual: System runs without SATA failure for more than 10 hours
Original-Change-Id: I8baa40935421769aeee341a78441fb19ecaa3206
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: https://chromium-review.googlesource.com/174648
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 49d25812b04a983d687a53a39530559ba99fd9b4)
Change-Id: Iac0b32f80958f5ffb571733484dc931bee216f55
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: https://chromium-review.googlesource.com/176352
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/6013
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/chip.h | 7 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/sata.c | 10 |
2 files changed, 14 insertions, 3 deletions
diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index 1b4ac2a355..e47a0310be 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -81,6 +81,13 @@ struct southbridge_intel_lynxpoint_config { */ uint8_t sata_devslp_mux; + /* + * DEVSLP Disable + * 0: DEVSLP is enabled + * 1: DEVSLP is disabled + */ + uint8_t sata_devslp_disable; + uint32_t gen1_dec; uint32_t gen2_dec; uint32_t gen3_dec; diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index a8d831955e..c2005402b1 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -172,10 +172,14 @@ static void sata_init(struct device *dev) /* CAP2 (HBA Capabilities Extended)*/ reg32 = read32(abar + 0x24); /* Enable DEVSLP */ - if (pch_is_lp()) - reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); - else + if (pch_is_lp()) { + if (config->sata_devslp_disable) + reg32 &= ~(1 << 3); + else + reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); + } else { reg32 &= ~0x00000002; + } write32(abar + 0x24, reg32); } else { printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); |