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| author | Sam McNally <sammc@chromium.org> | 2020-06-11 16:18:20 +1000 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-06-12 00:35:15 +0000 |
| commit | e36733bf849e781d6e86a7549f2c17d246e619ac (patch) | |
| tree | 10bc1fc49ec94cd5f967d0ede9c0beeacd32552a /src/southbridge/intel | |
| parent | 2048cb43863f014fedc4ff44233d49410f0cee5e (diff) | |
| download | coreboot-e36733bf849e781d6e86a7549f2c17d246e619ac.tar.xz | |
mb/google/puff: Update i2c[2] and i2c[3] rise and fall times
BRANCH=none
BUG=b:158713330
TEST=Flashing the LSPCON firmware works
Change-Id: Ib371f6954115145047c70cfd25262026cce087fd
Signed-off-by: Sam McNally <sammc@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Diffstat (limited to 'src/southbridge/intel')
0 files changed, 0 insertions, 0 deletions