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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-01-25 20:03:42 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-22 12:16:18 +0000 |
| commit | edbf5d913819726a09cd56bace2d13e74b560ab1 (patch) | |
| tree | cd33c998831b53e838e255565aba3b97fdbc8a69 /src/southbridge/intel | |
| parent | d30894b835eb466e6e46c64317edf96e5554b138 (diff) | |
| download | coreboot-edbf5d913819726a09cd56bace2d13e74b560ab1.tar.xz | |
cpu/intel/model_206ax: Use parallel MP init
This patch adds a few southbridge calls needed for parallel MP init.
Moves the smm_relocate() function to smm/gen1/smi.h, since that is
where this function is defined now.
Tested on Thinkpad X220, shaves off ~30ms on a 2 core, 4 threads CPU.
Change-Id: Ia1d547ed4a3cb6746a0222c3e54e94e5848b0dd7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25618
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/common/smi.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index af9dd5d87d..40f5412a91 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -154,3 +154,29 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1) "d" (APM_CNT) ); } + +void southbridge_smm_clear_state(void) +{ + u32 smi_en; + + if (IS_ENABLED(CONFIG_ELOG)) + /* Log events from chipset before clearing */ + pch_log_state(); + + printk(BIOS_DEBUG, "Initializing Southbridge SMI...\n"); + printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", get_pmbase()); + + smi_en = inl(get_pmbase() + SMI_EN); + if (smi_en & APMC_EN) { + printk(BIOS_INFO, "SMI# handler already enabled?\n"); + return; + } + + printk(BIOS_DEBUG, "\n"); + + /* Dump and clear status registers */ + reset_smi_status(); + reset_pm1_status(); + reset_tco_status(); + reset_gpe0_status(); +} |