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authorPatrick Rudolph <patrick.rudolph@9elements.com>2018-07-27 17:48:27 +0200
committerFelix Held <felix-coreboot@felixheld.de>2018-07-28 16:14:08 +0000
commitef8c559e537ed10d8054ca6a72ca50e0531fde95 (patch)
tree0244babea2d0833072841f672a7e571d9a57c720 /src/southbridge/intel
parent9e1b9b5a7e7eff660b6bfdee0e763e67be94bb6f (diff)
downloadcoreboot-ef8c559e537ed10d8054ca6a72ca50e0531fde95.tar.xz
nb/intel/sandybridge/report_platform: Move remaining code to sb folder
Change-Id: I2ced3f2bb9d1d150341a57ff333ca14c897c4fa3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c71
1 files changed, 71 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 611b08f734..d9e72b43ad 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -19,6 +19,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
+#include <device/pci_def.h>
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <pc80/i8259.h>
@@ -500,10 +501,80 @@ static void pch_spi_init(const struct device *const dev)
RCBA32_OR(0x3800 + 0xc4, 1 << 23); /* lock both UVSCC + LVSCC */
}
+static const struct {
+ u16 dev_id;
+ const char *dev_name;
+} pch_table[] = {
+ /* 6-series PCI ids from
+ * IntelĀ® 6 Series Chipset and
+ * IntelĀ® C200 Series Chipset
+ * Specification Update - NDA
+ * October 2013
+ * CDI / IBP#: 440377
+ */
+ {0x1C41, "SFF Sample"},
+ {0x1C42, "Desktop Sample"},
+ {0x1C43, "Mobile Sample"},
+ {0x1C44, "Z68"},
+ {0x1C46, "P67"},
+ {0x1C47, "UM67"},
+ {0x1C49, "HM65"},
+ {0x1C4A, "H67"},
+ {0x1C4B, "HM67"},
+ {0x1C4C, "Q65"},
+ {0x1C4D, "QS67"},
+ {0x1C4E, "Q67"},
+ {0x1C4F, "QM67"},
+ {0x1C50, "B65"},
+ {0x1C52, "C202"},
+ {0x1C54, "C204"},
+ {0x1C56, "C206"},
+ {0x1C5C, "H61"},
+ /* 7-series PCI ids from Intel document 472178 */
+ {0x1E41, "Desktop Sample"},
+ {0x1E42, "Mobile Sample"},
+ {0x1E43, "SFF Sample"},
+ {0x1E44, "Z77"},
+ {0x1E45, "H71"},
+ {0x1E46, "Z75"},
+ {0x1E47, "Q77"},
+ {0x1E48, "Q75"},
+ {0x1E49, "B75"},
+ {0x1E4A, "H77"},
+ {0x1E53, "C216"},
+ {0x1E55, "QM77"},
+ {0x1E56, "QS77"},
+ {0x1E58, "UM77"},
+ {0x1E57, "HM77"},
+ {0x1E59, "HM76"},
+ {0x1E5D, "HM75"},
+ {0x1E5E, "HM70"},
+ {0x1E5F, "NM70"},
+};
+
+static void report_pch_info(struct device *dev)
+{
+ const u16 dev_id = pci_read_config16(dev, PCI_DEVICE_ID);
+ int i;
+
+ const char *pch_type = "Unknown";
+ for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
+ if (pch_table[i].dev_id == dev_id) {
+ pch_type = pch_table[i].dev_name;
+ break;
+ }
+ }
+ printk(BIOS_INFO, "PCH: detected %s, device id: 0x%x, rev id 0x%x\n",
+ pch_type, dev_id, pci_read_config8(dev, PCI_CLASS_REVISION));
+}
+
static void lpc_init(struct device *dev)
{
printk(BIOS_DEBUG, "pch: lpc_init\n");
+ /* Print detected platform */
+ report_pch_info(dev);
+
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND, 0x000f);