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| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-02-05 15:03:50 +0100 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-09-13 21:53:27 +0200 |
| commit | 0650cd0bad2816886745c4a7ffe0e7a1aefb9957 (patch) | |
| tree | 5db1d13c75167c0203bcaa0d139a446ad2004772 /src/southbridge/intel | |
| parent | 76998336aa82b692c1b0cf1e2427602b5b655fac (diff) | |
| download | coreboot-0650cd0bad2816886745c4a7ffe0e7a1aefb9957.tar.xz | |
southbridge/bd82x6x: Reserve 16 MiB for flash and not 8.
X230 has 12 MiB flash. SPI controller supports up to 2 x 16 MiB of flash
but address map limits this to 16MiB.
Change-Id: Icc39c3c8d45d2d14e437bdfce920f8b4b039789d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5133
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/lpc.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 396b771e81..fa05d54097 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -597,8 +597,11 @@ static void pch_lpc_read_resources(device_t dev) IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ + res->base = 0xff000000; + /* Some systems (e.g. X230) have 12 MiB flash. + SPI controller supports up to 2 x 16 MiB of flash but + address map limits this to 16MiB. */ + res->size = 0x01000000; /* 16 MB for flash */ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |