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| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-09-19 22:07:33 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-09-22 09:48:33 +0000 |
| commit | 853c1afac21f3cfd19f487e95ba2b53cbd80e241 (patch) | |
| tree | a95f2be5d13810abe5aba49db529c464390e95c6 /src/southbridge/intel | |
| parent | 5a7dc9eb6212ef65c93ddb1493ba3a1d660929ed (diff) | |
| download | coreboot-853c1afac21f3cfd19f487e95ba2b53cbd80e241.tar.xz | |
mb/supermicro/x11ssh: remove unnecessary fsp setting CdClock
CdClock does not need to be set because the board does not use IGD.
Change-Id: I6835ccdf80530f9efc6fdeb0363dcf9267f99d21
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel')
0 files changed, 0 insertions, 0 deletions