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authorAngel Pons <th3fanbus@gmail.com>2020-06-01 19:31:53 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-21 18:22:52 +0000
commit90e9f5472680bbc44fe4e23b390a9323f8c59643 (patch)
treeada8a2e33d2cb3a125f6e86d807d443409e814d7 /src/southbridge/intel
parent492d801aabeecf2dbf0787784bbb97ab2a901dcc (diff)
downloadcoreboot-90e9f5472680bbc44fe4e23b390a9323f8c59643.tar.xz
ironlake/ibexpeak: Move early_smbus.c to common code
We will update the other platforms to use this common code in susbsequent commits. While we are at it, reflow a broken line, define the SMBus PCI device in the header and fix whitespace. Change-Id: I1fdff2feead4165f02b24cb948d8c03318969014 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41999 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/common/Kconfig3
-rw-r--r--src/southbridge/intel/common/Makefile.inc2
-rw-r--r--src/southbridge/intel/common/early_smbus.c (renamed from src/southbridge/intel/ibexpeak/early_smbus.c)9
-rw-r--r--src/southbridge/intel/common/early_smbus.h18
-rw-r--r--src/southbridge/intel/ibexpeak/Kconfig1
-rw-r--r--src/southbridge/intel/ibexpeak/Makefile.inc1
6 files changed, 28 insertions, 6 deletions
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig
index 195e71579c..3030d25757 100644
--- a/src/southbridge/intel/common/Kconfig
+++ b/src/southbridge/intel/common/Kconfig
@@ -15,6 +15,9 @@ config SOUTHBRIDGE_INTEL_COMMON_PMBASE
config SOUTHBRIDGE_INTEL_COMMON_GPIO
def_bool n
+config SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
+ def_bool n
+
config SOUTHBRIDGE_INTEL_COMMON_SMBUS
def_bool n
select HAVE_DEBUG_SMBUS
diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc
index b3c48fa99c..1ededd23ec 100644
--- a/src/southbridge/intel/common/Makefile.inc
+++ b/src/southbridge/intel/common/Makefile.inc
@@ -5,6 +5,8 @@ subdirs-y += firmware
all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
+romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS) += early_smbus.c
+
romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/common/early_smbus.c
index 85f20a745c..d65b4aaf81 100644
--- a/src/southbridge/intel/ibexpeak/early_smbus.c
+++ b/src/southbridge/intel/common/early_smbus.c
@@ -1,10 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <device/pci_def.h>
#include <device/smbus_host.h>
-#include "pch.h"
+#include "early_smbus.h"
uintptr_t smbus_base(void)
{
@@ -14,15 +14,14 @@ uintptr_t smbus_base(void)
int smbus_enable_iobar(uintptr_t base)
{
/* Set the SMBus device statically. */
- pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
+ const pci_devfn_t dev = PCI_DEV_SMBUS;
/* Check to make sure we've got the right device. */
if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL)
return -1;
/* Set SMBus I/O base. */
- pci_write_config32(dev, SMB_BASE,
- base | PCI_BASE_ADDRESS_SPACE_IO);
+ pci_write_config32(dev, SMB_BASE, base | PCI_BASE_ADDRESS_SPACE_IO);
/* Set SMBus enable. */
pci_write_config8(dev, HOSTC, HST_EN);
diff --git a/src/southbridge/intel/common/early_smbus.h b/src/southbridge/intel/common/early_smbus.h
new file mode 100644
index 0000000000..d6a7cbbcce
--- /dev/null
+++ b/src/southbridge/intel/common/early_smbus.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS_H
+#define SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS_H
+
+#include <device/pci_def.h>
+
+#define PCI_DEV_SMBUS PCI_DEV(0, 0x1f, 3)
+
+#define SMB_BASE PCI_BASE_ADDRESS_4
+#define HOSTC 0x40
+
+/* HOSTC bits */
+#define I2C_EN (1 << 2)
+#define SMB_SMI_EN (1 << 1)
+#define HST_EN (1 << 0)
+
+#endif /* SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS_H */
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index 691459e906..07f9b6b110 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -16,6 +16,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_COMMON_FINALIZE
select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
+ select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
select SOUTHBRIDGE_INTEL_COMMON_SMM
select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc
index d8de593e93..a146187918 100644
--- a/src/southbridge/intel/ibexpeak/Makefile.inc
+++ b/src/southbridge/intel/ibexpeak/Makefile.inc
@@ -28,7 +28,6 @@ ramstage-y += madt.c
smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c
romstage-y += early_pch.c
-romstage-y += early_smbus.c
romstage-y +=../bd82x6x/early_me.c
romstage-y +=../bd82x6x/me_status.c
romstage-y += early_thermal.c