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authorKeith Hui <buurin@gmail.com>2017-11-14 18:48:34 -0500
committerStefan Reinauer <stefan.reinauer@coreboot.org>2017-12-07 19:20:26 +0000
commit97041de909b5468c1a62afd5e38bf59c6b5c7881 (patch)
treee6cec725afc6f11919e50c38ee689786e5dd96f8 /src/southbridge/intel
parent9d0aa99c5ef1ffb4458f6a3070444cf8bf572ccd (diff)
downloadcoreboot-97041de909b5468c1a62afd5e38bf59c6b5c7881.tar.xz
sb/intel/i82371eb: Rework ACPI tables
Rework ACPI tables based on a mix of previous work on asus/p2b, other boards in tree with better ACPI support, and OEM BIOS. To be pulled in by DSDTs of mainboards using this southbridge. Disable on-the-fly generation of mainboard _CRS node. It is not working as it should and causes runtime errors when booting Linux. This node to be included in mainboard DSDTs in followup patches. Change-Id: Idda424de7859a36e4cac168d5469f9365a6ad421 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/i82371eb/acpi/i82371eb.asl95
-rw-r--r--src/southbridge/intel/i82371eb/acpi/intx.asl60
2 files changed, 155 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl
new file mode 100644
index 0000000000..305da2a8dd
--- /dev/null
+++ b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl
@@ -0,0 +1,95 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2017 Keith Hui <buurin@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Declares assorted devices that falls under this southbridge.
+ */
+#include "southbridge/intel/i82371eb/i82371eb.h"
+
+ OperationRegion (S1XX, PCI_Config, 0xB2, 0x01)
+ Field (S1XX, ByteAcc, NoLock, Preserve)
+ {
+ FXS1, 8
+ }
+
+ /* 8259-compatible Programmable Interrupt Controller */
+ Device (PIC)
+ {
+ Name (_HID, EisaId ("PNP0000") )
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0020, 0x0020, 0x01, 0x02, )
+ IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02, )
+ IRQNoFlags () {2}
+ })
+ }
+
+ /* PC-class DMA Controller */
+ Device (DMA1)
+ {
+ Name (_HID, EisaId ("PNP0200") )
+ Name (_CRS, ResourceTemplate ()
+ {
+ DMA (Compatibility, BusMaster, Transfer8, ) {4}
+ IO (Decode16, 0x0000, 0x0000, 0x01, 0x10,)
+ IO (Decode16, 0x0080, 0x0080, 0x01, 0x11,)
+ IO (Decode16, 0x0094, 0x0094, 0x01, 0x0C,)
+ IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20,)
+ })
+ }
+
+ /* PC-class System Timer */
+ Device (TMR)
+ {
+ Name (_HID, EisaId ("PNP0100"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16,0x0040,0x0040,0x01,0x04,)
+ IRQNoFlags () {0}
+ })
+ }
+
+ /* AT Real-Time Clock */
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00") )
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16,0x0070,0x0070,0x01,0x04,)
+ IRQNoFlags () {8}
+ })
+ }
+
+ Device (SPKR)
+ {
+ Name (_HID, EisaId ("PNP0800"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16,0x0061,0x0061,0x01,0x01,)
+ })
+ }
+
+ /* x87-compatible Floating Point Processing Unit */
+ Device (COPR)
+ {
+ Name (_HID, EisaId ("PNP0C04") )
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16,0x00F0,0x00F0,0x01,0x10,)
+ IRQNoFlags () {13}
+ })
+ }
diff --git a/src/southbridge/intel/i82371eb/acpi/intx.asl b/src/southbridge/intel/i82371eb/acpi/intx.asl
new file mode 100644
index 0000000000..97e67037ff
--- /dev/null
+++ b/src/southbridge/intel/i82371eb/acpi/intx.asl
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+Name(IRQB, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Shared){}
+})
+
+Name(IRQP, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Shared){3, 4, 5, 6, 7, 10, 11, 12, 14, 15}
+})
+
+/* adapted from ma78gm/dsdt.asl */
+#define PCI_INTX_DEV(intx, pinx, uid) \
+Device(intx) { \
+ Name(_HID, EISAID("PNP0C0F")) \
+ Name(_UID, uid) \
+ \
+ Method(_STA, 0) { \
+ If (And(pinx, 0x80)) { \
+ Return(0x09) \
+ } \
+ Return(0x0B) \
+ } \
+ \
+ Method(_DIS ,0) { \
+ Store(0x80, pinx) \
+ } \
+ \
+ Method(_PRS ,0) { \
+ Return(IRQP) \
+ } \
+ \
+ Method(_CRS ,0) { \
+ CreateWordField(IRQB, 1, IRQN) \
+ ShiftLeft(1, And(pinx, 0x0f), IRQN) \
+ Return(IRQB) \
+ } \
+ \
+ Method(_SRS, 1) { \
+ CreateWordField(ARG0, 1, IRQM) \
+ \
+ /* Use lowest available IRQ */ \
+ FindSetRightBit(IRQM, Local0) \
+ if (Local0) { \
+ Decrement(Local0) \
+ } \
+ Store(Local0, pinx) \
+ } \
+} \