summaryrefslogtreecommitdiff
path: root/src/southbridge/intel
diff options
context:
space:
mode:
authorMartin Roth <martinroth@google.com>2017-07-21 10:23:57 -0600
committerMartin Roth <martinroth@google.com>2017-07-21 17:00:01 +0000
commitb137c13e57c667db861abc57dffe079ceaeea8c1 (patch)
treeb56ad68f0657142c905b7855061b23a3cc611e09 /src/southbridge/intel
parent837afb0938cfa951290d252e1e37adff8fff9f5a (diff)
downloadcoreboot-b137c13e57c667db861abc57dffe079ceaeea8c1.tar.xz
I82801JX: Add IS_ENABLED around config options
This chipset was just added and had a few places that needed to be fixed. Change-Id: Ief048c4876c5a2cb538c9cb4b295aba46a4fff62 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20684 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/i82801jx/acpi/sleepstates.asl2
-rw-r--r--src/southbridge/intel/i82801jx/i82801jx.c2
-rw-r--r--src/southbridge/intel/i82801jx/lpc.c4
3 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/intel/i82801jx/acpi/sleepstates.asl b/src/southbridge/intel/i82801jx/acpi/sleepstates.asl
index 62bb0264de..d7fb2a56bb 100644
--- a/src/southbridge/intel/i82801jx/acpi/sleepstates.asl
+++ b/src/southbridge/intel/i82801jx/acpi/sleepstates.asl
@@ -15,7 +15,7 @@
*/
Name(\_S0, Package(){0x0,0x0,0x0,0x0})
-#if !CONFIG_HAVE_ACPI_RESUME
+#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
Name(\_S1, Package(){0x1,0x0,0x0,0x0})
#else
Name(\_S3, Package(){0x5,0x0,0x0,0x0})
diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c
index dca3a4142e..644524d1f4 100644
--- a/src/southbridge/intel/i82801jx/i82801jx.c
+++ b/src/southbridge/intel/i82801jx/i82801jx.c
@@ -222,7 +222,7 @@ static void i82801jx_init(void *chip_info)
i82801jx_hide_functions();
/* Reset watchdog timer. */
-#if !CONFIG_HAVE_SMI_HANDLER
+#if !IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */
#endif
outw(0x0000, DEFAULT_TCOBASE + 0x00); /* Update timer. */
diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c
index 5d3b6b5d65..edbd0e87d3 100644
--- a/src/southbridge/intel/i82801jx/lpc.c
+++ b/src/southbridge/intel/i82801jx/lpc.c
@@ -369,7 +369,7 @@ static void enable_clock_gating(void)
RCBA32(0x38c0) |= 7;
}
-#if CONFIG_HAVE_SMI_HANDLER
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
static void i82801jx_lock_smm(struct device *dev)
{
#if TEST_SMM_FLASH_LOCKDOWN
@@ -464,7 +464,7 @@ static void lpc_init(struct device *dev)
/* Interrupt 9 should be level triggered (SCI) */
i8259_configure_irq_trigger(9, 1);
-#if CONFIG_HAVE_SMI_HANDLER
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
i82801jx_lock_smm(dev);
#endif
}