sb/intel/i82801ex: Remove unused code

Only board using this code was tyan s2735 which was removed in
f76de841f1 "[REMOVAL] tyan/s2735"

Change-Id: I03a101adc1eedfa9669e0b44c54c2c6fa08bd5f2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>

17 files changed, 0 insertions, 1120 deletions

diff --git a/src/southbridge/intel/i82801ex/Kconfig b/src/southbridge/intel/i82801ex/Kconfig
deleted file mode 100644
index caa5c79ad9..0000000000
--- a/src/southbridge/intel/i82801ex/Kconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-config SOUTHBRIDGE_INTEL_I82801EX
-	bool
-	select SOUTHBRIDGE_INTEL_COMMON
-	select IOAPIC
-	select HAVE_HARD_RESET
-	select HAVE_USBDEBUG
-
-if SOUTHBRIDGE_INTEL_I82801EX
-
-config EHCI_BAR
-	hex
-	default 0xfef00000
-
-endif
diff --git a/src/southbridge/intel/i82801ex/Makefile.inc b/src/southbridge/intel/i82801ex/Makefile.inc
deleted file mode 100644
index 240eaf0517..0000000000
--- a/src/southbridge/intel/i82801ex/Makefile.inc
+++ /dev/null
@@ -1,15 +0,0 @@
-ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801EX),y)
-
-ramstage-y += i82801ex.c
-ramstage-y += uhci.c
-ramstage-y += lpc.c
-ramstage-y += ide.c
-ramstage-y += sata.c
-ramstage-y += ehci.c
-ramstage-y += smbus.c
-ramstage-y += pci.c
-ramstage-y += ac97.c
-ramstage-y += watchdog.c
-ramstage-y += reset.c
-
-endif
diff --git a/src/southbridge/intel/i82801ex/ac97.c b/src/southbridge/intel/i82801ex/ac97.c
deleted file mode 100644
index 08efe1534d..0000000000
--- a/src/southbridge/intel/i82801ex/ac97.c
+++ /dev/null
@@ -1,37 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "i82801ex.h"
-
-static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device)
-{
-	/* Write the subsystem vendor and device id */
-	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
-		((device & 0xffff) << 16) | (vendor & 0xffff));
-}
-
-static struct pci_operations lops_pci = {
-	.set_subsystem = ac97_set_subsystem,
-};
-static struct device_operations ac97_ops  = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = 0,
-	.scan_bus         = 0,
-	.enable           = i82801ex_enable,
-	.ops_pci          = &lops_pci,
-};
-
-static const struct pci_driver ac97_audio_driver __pci_driver = {
-	.ops    = &ac97_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801ER_AC97_AUDIO,
-};
-static const struct pci_driver ac97_modem_driver __pci_driver = {
-	.ops    = &ac97_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801ER_AC97_MODEM,
-};
diff --git a/src/southbridge/intel/i82801ex/chip.h b/src/southbridge/intel/i82801ex/chip.h
deleted file mode 100644
index 291fcd7d41..0000000000
--- a/src/southbridge/intel/i82801ex/chip.h
+++ /dev/null
@@ -1,34 +0,0 @@
-#ifndef I82801EX_CHIP_H
-#define I82801EX_CHIP_H
-
-struct southbridge_intel_i82801ex_config
-{
-
-#define ICH5R_GPIO_USE_MASK      0x03
-#define ICH5R_GPIO_USE_DEFAULT   0x00
-#define ICH5R_GPIO_USE_AS_NATIVE 0x01
-#define ICH5R_GPIO_USE_AS_GPIO   0x02
-
-#define ICH5R_GPIO_SEL_MASK      0x0c
-#define ICH5R_GPIO_SEL_DEFAULT   0x00
-#define ICH5R_GPIO_SEL_OUTPUT    0x04
-#define ICH5R_GPIO_SEL_INPUT     0x08
-
-#define ICH5R_GPIO_LVL_MASK      0x30
-#define ICH5R_GPIO_LVL_DEFAULT   0x00
-#define ICH5R_GPIO_LVL_LOW       0x10
-#define ICH5R_GPIO_LVL_HIGH      0x20
-#define ICH5R_GPIO_LVL_BLINK     0x30
-
-#define ICH5R_GPIO_INV_MASK      0xc0
-#define ICH5R_GPIO_INV_DEFAULT   0x00
-#define ICH5R_GPIO_INV_OFF       0x40
-#define ICH5R_GPIO_INV_ON        0x80
-
-	/* GPIO use select */
-	unsigned char gpio[64];
-	unsigned int  pirq_a_d;
-	unsigned int  pirq_e_h;
-};
-
-#endif /* I82801EX_CHIP_H */
diff --git a/src/southbridge/intel/i82801ex/early_smbus.c b/src/southbridge/intel/i82801ex/early_smbus.c
deleted file mode 100644
index ad543e7a94..0000000000
--- a/src/southbridge/intel/i82801ex/early_smbus.c
+++ /dev/null
@@ -1,130 +0,0 @@
-#include "smbus.h"
-
-#define SMBUS_IO_BASE 0x0f00
-
-static void enable_smbus(void)
-{
-	device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
-
-	printk(BIOS_SPEW, "SMBus controller enabled\n");
-
-	pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
-	printk(BIOS_DEBUG, "%08x", pci_read_config32(dev, 0x20));
-	/* Set smbus enable */
-	pci_write_config8(dev, 0x40, 1);
-	/* Set smbus iospace enable */
-	pci_write_config8(dev, 0x4, 1);
-	/* SMBALERT_DIS */
-	pci_write_config8(dev, 0x11, 4);
-
-	/* Disable interrupt generation */
-	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
-
-	/* clear any lingering errors, so the transaction will run */
-	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-}
-
-static int smbus_read_byte(unsigned device, unsigned address)
-{
-	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
-
-#ifdef UNUSED_CODE
-static void smbus_write_byte(unsigned device, unsigned address, unsigned char val)
-{
-	if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
-		return;
-	}
-
-	printk(BIOS_DEBUG, "Unimplemented smbus_write_byte() called.\n");
-
-#if 0
-	/* setup transaction */
-	/* disable interrupts */
-	outw(inw(SMBUS_IO_BASE + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)),
-			SMBUS_IO_BASE + SMBGCTL);
-	/* set the device I'm talking too */
-	outw(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADDR);
-	outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
-	/* set up for a byte data write */ /* FIXME */
-	outw((inw(SMBUS_IO_BASE + SMBGCTL) & ~7) | (0x1), SMBUS_IO_BASE + SMBGCTL);
-	/* clear any lingering errors, so the transaction will run */
-	/* Do I need to write the bits to a 1 to clear an error? */
-	outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
-
-	/* clear the data word...*/
-	outw(val, SMBUS_IO_BASE + SMBHSTDAT);
-
-	/* start the command */
-	outw((inw(SMBUS_IO_BASE + SMBGCTL) | (1 << 3)), SMBUS_IO_BASE + SMBGCTL);
-
-	/* poll for transaction completion */
-	smbus_wait_until_done(SMBUS_IO_BASE);
-#endif
-	return;
-}
-
-static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
-		 unsigned data1, unsigned data2)
-{
-	unsigned char byte;
-	unsigned char stat;
-	int i;
-
-	/* chear the PM timeout flags, SECOND_TO_STS */
-	outw(inw(0x0400 + 0x66), 0x0400 + 0x66);
-
-	if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
-		return -2;
-	}
-
-	/* setup transaction */
-	/* Obtain ownership */
-	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-	for (stat=0;(stat&0x40)==0;) {
-	stat = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-	}
-	/* clear the done bit */
-	outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT);
-	/* disable interrupts */
-	outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
-
-	/* set the device I'm talking too */
-	outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD);
-
-	/* set the command address */
-	outb(cmd & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
-
-	/* set the block length */
-	outb(length & 0xFF, SMBUS_IO_BASE + SMBHSTDAT0);
-
-	/* try sending out the first byte of data here */
-	byte=(data1>>(0))&0x0ff;
-	outb(byte,SMBUS_IO_BASE + SMBBLKDAT);
-	/* issue a block write command */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40,
-			SMBUS_IO_BASE + SMBHSTCTL);
-
-	for (i=0;i<length;i++) {
-
-		/* poll for transaction completion */
-		if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) {
-			return -3;
-		}
-
-		/* load the next byte */
-		if (i>3)
-			byte=(data2>>(i%4))&0x0ff;
-		else
-			byte=(data1>>(i))&0x0ff;
-		outb(byte,SMBUS_IO_BASE + SMBBLKDAT);
-
-		/* clear the done bit */
-		outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
-				SMBUS_IO_BASE + SMBHSTSTAT);
-	}
-
-	printk(BIOS_DEBUG, "SMBUS Block complete\n");
-	return 0;
-}
-#endif
diff --git a/src/southbridge/intel/i82801ex/ehci.c b/src/southbridge/intel/i82801ex/ehci.c
deleted file mode 100644
index 28164c5594..0000000000
--- a/src/southbridge/intel/i82801ex/ehci.c
+++ /dev/null
@@ -1,51 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <device/pci_ehci.h>
-#include "i82801ex.h"
-
-static void ehci_init(struct device *dev)
-{
-	uint32_t cmd;
-
-	printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
-	cmd = pci_read_config32(dev, PCI_COMMAND);
-	pci_write_config32(dev, PCI_COMMAND,
-		cmd | PCI_COMMAND_MASTER);
-
-	printk(BIOS_DEBUG, "done.\n");
-}
-
-static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
-{
-	uint8_t access_cntl;
-	access_cntl = pci_read_config8(dev, 0x80);
-	/* Enable writes to protected registers */
-	pci_write_config8(dev, 0x80, access_cntl | 1);
-	/* Write the subsystem vendor and device id */
-	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
-		((device & 0xffff) << 16) | (vendor & 0xffff));
-	/* Restore protection */
-	pci_write_config8(dev, 0x80, access_cntl);
-}
-
-static struct pci_operations lops_pci = {
-	.set_subsystem = &ehci_set_subsystem,
-};
-static struct device_operations ehci_ops  = {
-	.read_resources   = pci_ehci_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = ehci_init,
-	.scan_bus         = 0,
-	.enable           = i82801ex_enable,
-	.ops_pci          = &lops_pci,
-};
-
-static const struct pci_driver ehci_driver __pci_driver = {
-	.ops    = &ehci_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801ER_EHCI,
-};
diff --git a/src/southbridge/intel/i82801ex/i82801ex.c b/src/southbridge/intel/i82801ex/i82801ex.c
deleted file mode 100644
index e01832059a..0000000000
--- a/src/southbridge/intel/i82801ex/i82801ex.c
+++ /dev/null
@@ -1,48 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "i82801ex.h"
-
-void i82801ex_enable(device_t dev)
-{
-	device_t lpc_dev;
-	unsigned index = 0;
-	uint16_t reg_old, reg;
-
-	/* See if we are behind the i82801ex pci bridge */
-	lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0));
-	if ((dev->path.pci.devfn &0xf8)== 0xf8) {
-		index = dev->path.pci.devfn & 7;
-	}
-	else if ((dev->path.pci.devfn &0xf8)== 0xe8) {
-		index = (dev->path.pci.devfn & 7) +8;
-	}
-	if ((!lpc_dev) || (index >= 16) || ((1<<index)&0x3091)) {
-		return;
-	}
-	if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) ||
-		(lpc_dev->device != PCI_DEVICE_ID_INTEL_82801ER_LPC)) {
-		uint32_t id;
-		id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
-		if (id != (PCI_VENDOR_ID_INTEL |
-				(PCI_DEVICE_ID_INTEL_82801ER_LPC << 16))) {
-			return;
-		}
-	}
-
-	reg = reg_old = pci_read_config16(lpc_dev, 0xf2);
-	reg &= ~(1 << index);
-	if (!dev->enabled) {
-		reg |= (1 << index);
-	}
-	if (reg != reg_old) {
-		pci_write_config16(lpc_dev, 0xf2, reg);
-	}
-
-}
-
-struct chip_operations southbridge_intel_i82801ex_ops = {
-	CHIP_NAME("Intel ICH5 (82801Ex) Series Southbridge")
-	.enable_dev = i82801ex_enable,
-};
diff --git a/src/southbridge/intel/i82801ex/i82801ex.h b/src/southbridge/intel/i82801ex/i82801ex.h
deleted file mode 100644
index 3c7321a9fa..0000000000
--- a/src/southbridge/intel/i82801ex/i82801ex.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef I82801EX_H
-#define I82801EX_H
-
-#include "chip.h"
-
-extern void i82801ex_enable(device_t dev);
-
-#define PCI_DMA_CFG     0x90
-#define SERIRQ_CNTL     0x64
-#define GEN_CNTL        0xd0
-#define GEN_STS         0xd4
-#define RTC_CONF        0xd8
-#define GEN_PMCON_3     0xa4
-
-#define PMBASE          0x40
-#define ACPI_CNTL       0x44
-#define   ACPI_EN	(1 << 4)
-#define GPIO_BASE       0x58
-#define GPIO_CNTL       0x5C
-#define   GPIO_EN	(1 << 4)
-
-#endif /* I82801EX_H */
diff --git a/src/southbridge/intel/i82801ex/ide.c b/src/southbridge/intel/i82801ex/ide.c
deleted file mode 100644
index 542c5944e1..0000000000
--- a/src/southbridge/intel/i82801ex/ide.c
+++ /dev/null
@@ -1,42 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "i82801ex.h"
-
-static void ide_init(struct device *dev)
-{
-	/* Enable IDE devices and timmings */
-	pci_write_config16(dev, 0x40, 0x0a307); // IDE0
-	pci_write_config16(dev, 0x42, 0x0a307); // IDE1
-	pci_write_config8(dev, 0x48, 0x05);
-	pci_write_config16(dev, 0x4a, 0x0101);
-	pci_write_config16(dev, 0x54, 0x5055);
-	printk(BIOS_DEBUG, "IDE Enabled\n");
-}
-
-static void i82801ex_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
-{
-	/* This value is also visible in uchi[0-2] and smbus functions */
-	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
-		((device & 0xffff) << 16) | (vendor & 0xffff));
-}
-
-static struct pci_operations lops_pci = {
-	.set_subsystem = i82801ex_ide_set_subsystem,
-};
-static struct device_operations ide_ops  = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = ide_init,
-	.scan_bus         = 0,
-	.ops_pci          = &lops_pci,
-};
-
-static const struct pci_driver ide_driver __pci_driver = {
-	.ops    = &ide_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801ER_IDE,
-};
diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c
deleted file mode 100644
index 7d01dbc4ba..0000000000
--- a/src/southbridge/intel/i82801ex/lpc.c
+++ /dev/null
@@ -1,381 +0,0 @@
-/*
- * (C) 2004 Linux Networx
- */
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <pc80/mc146818rtc.h>
-#include <pc80/isa-dma.h>
-#include <arch/io.h>
-#include <arch/ioapic.h>
-#include "i82801ex.h"
-
-
-#define NMI_OFF 0
-#define MAINBOARD_POWER_OFF 0
-#define MAINBOARD_POWER_ON  1
-
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
-/**
- * Enable ACPI I/O range.
- *
- * @param dev PCI device with ACPI and PM BAR's
- */
-static void i82801ex_enable_acpi(struct device *dev)
-{
-	u8 gpio_cntl;
-
-	/* Enable ACPI I/O range decode and ACPI power management. */
-	pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
-
-	/* Enable the GPIO bar */
-	gpio_cntl = pci_read_config8(dev, GPIO_CNTL);
-	gpio_cntl |= GPIO_EN;
-	pci_write_config8(dev, GPIO_CNTL, gpio_cntl);
-}
-
-/**
- * Set miscellanous static southbridge features.
- *
- * @param dev PCI device with I/O APIC configuration registers
- */
-static void i82801ex_general_cntl(struct device *dev)
-{
-	u32 reg32;
-
-	reg32 = pci_read_config32(dev, GEN_CNTL);
-	reg32 |= (3 << 7);	/* IOAPIC enable (APIC_EN) */
-	reg32 |= (1 << 1);	/* Delayed transaction enable (DTE) */
-	pci_write_config32(dev, GEN_CNTL, reg32);
-	printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32);
-
-	reg32 = pci_read_config32(dev, GEN_STS);
-	reg32 |= (1<<1);
-	pci_write_config32(dev, GEN_STS, reg32);
-
-}
-
-#define SERIRQ_CNTL 0x64
-static void i82801ex_enable_serial_irqs(device_t dev)
-{
-	/* set packet length and toggle silent mode bit */
-	pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0));
-	pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(0 << 6)|((21 - 17) << 2)|(0 << 0));
-}
-
-#define PCI_DMA_CFG 0x90
-static void i82801ex_pci_dma_cfg(device_t dev)
-{
-	/* Set PCI DMA CFG to lpc I/F DMA */
-	pci_write_config16(dev, PCI_DMA_CFG, 0xfcff);
-}
-
-#define LPC_EN 0xe6
-static void i82801ex_enable_lpc(device_t dev)
-{
-	/* lpc i/f enable */
-	pci_write_config8(dev, LPC_EN, 0x0d);
-}
-
-typedef struct southbridge_intel_i82801ex_config config_t;
-
-static void set_i82801ex_gpio_use_sel(
-	device_t dev, struct resource *res, config_t *config)
-{
-	uint32_t gpio_use_sel, gpio_use_sel2;
-	int i;
-
-	gpio_use_sel  = 0x1A003180;
-	gpio_use_sel2 = 0x00000007;
-	for (i = 0; i < 64; i++) {
-		int val;
-		switch(config->gpio[i] & ICH5R_GPIO_USE_MASK) {
-		case ICH5R_GPIO_USE_AS_NATIVE: val = 0; break;
-		case ICH5R_GPIO_USE_AS_GPIO:   val = 1; break;
-		default:
-			continue;
-		}
-		/* The caller is responsible for not playing with unimplemented bits */
-		if (i < 32) {
-			gpio_use_sel  &= ~( 1 << i);
-			gpio_use_sel  |= (val << i);
-		} else {
-			gpio_use_sel2 &= ~( 1 << (i - 32));
-			gpio_use_sel2 |= (val << (i - 32));
-		}
-	}
-	outl(gpio_use_sel,  res->base + 0x00);
-	outl(gpio_use_sel2, res->base + 0x30);
-}
-
-static void set_i82801ex_gpio_direction(
-	device_t dev, struct resource *res, config_t *config)
-{
-	uint32_t gpio_io_sel, gpio_io_sel2;
-	int i;
-
-	gpio_io_sel  = 0x0000ffff;
-	gpio_io_sel2 = 0x00000300;
-	for (i = 0; i < 64; i++) {
-		int val;
-		switch(config->gpio[i] & ICH5R_GPIO_SEL_MASK) {
-		case ICH5R_GPIO_SEL_OUTPUT: val = 0; break;
-		case ICH5R_GPIO_SEL_INPUT:  val = 1; break;
-		default:
-			continue;
-		}
-		/* The caller is responsible for not playing with unimplemented bits */
-		if (i < 32) {
-			gpio_io_sel  &= ~( 1 << i);
-			gpio_io_sel  |= (val << i);
-		} else {
-			gpio_io_sel2 &= ~( 1 << (i - 32));
-			gpio_io_sel2 |= (val << (i - 32));
-		}
-	}
-	outl(gpio_io_sel,  res->base + 0x04);
-	outl(gpio_io_sel2, res->base + 0x34);
-}
-
-static void set_i82801ex_gpio_level(
-	device_t dev, struct resource *res, config_t *config)
-{
-	uint32_t gpio_lvl, gpio_lvl2;
-	uint32_t gpio_blink;
-	int i;
-
-	gpio_lvl   = 0x1b3f0000;
-	gpio_blink = 0x00040000;
-	gpio_lvl2  = 0x00030207;
-	for (i = 0; i < 64; i++) {
-		int val, blink;
-		switch(config->gpio[i] & ICH5R_GPIO_LVL_MASK) {
-		case ICH5R_GPIO_LVL_LOW:   val = 0; blink = 0; break;
-		case ICH5R_GPIO_LVL_HIGH:  val = 1; blink = 0; break;
-		case ICH5R_GPIO_LVL_BLINK: val = 1; blink = 1; break;
-		default:
-			continue;
-		}
-		/* The caller is responsible for not playing with unimplemented bits */
-		if (i < 32) {
-			gpio_lvl   &= ~(   1 << i);
-			gpio_blink &= ~(   1 << i);
-			gpio_lvl   |= (  val << i);
-			gpio_blink |= (blink << i);
-		} else {
-			gpio_lvl2  &= ~( 1 << (i - 32));
-			gpio_lvl2  |= (val << (i - 32));
-		}
-	}
-	outl(gpio_lvl,   res->base + 0x0c);
-	outl(gpio_blink, res->base + 0x18);
-	outl(gpio_lvl2,  res->base + 0x38);
-}
-
-static void set_i82801ex_gpio_inv(
-	device_t dev, struct resource *res, config_t *config)
-{
-	uint32_t gpio_inv;
-	int i;
-
-	gpio_inv   = 0x00000000;
-	for (i = 0; i < 32; i++) {
-		int val;
-		switch(config->gpio[i] & ICH5R_GPIO_INV_MASK) {
-		case ICH5R_GPIO_INV_OFF: val = 0; break;
-		case ICH5R_GPIO_INV_ON:  val = 1; break;
-		default:
-			continue;
-		}
-		gpio_inv &= ~( 1 << i);
-		gpio_inv |= (val << i);
-	}
-	outl(gpio_inv,   res->base + 0x2c);
-}
-
-static void i82801ex_pirq_init(device_t dev)
-{
-	config_t *config;
-
-	/* Get the chip configuration */
-	config = dev->chip_info;
-
-	if (config->pirq_a_d) {
-		pci_write_config32(dev, 0x60, config->pirq_a_d);
-	}
-	if (config->pirq_e_h) {
-		pci_write_config32(dev, 0x68, config->pirq_e_h);
-	}
-}
-
-
-static void i82801ex_gpio_init(device_t dev)
-{
-	struct resource *res;
-	config_t *config;
-
-	/* Skip if I don't have any configuration */
-	if (!dev->chip_info) {
-		return;
-	}
-	/* The programmer is responsible for ensuring
-	 * a valid gpio configuration.
-	 */
-
-	/* Get the chip configuration */
-	config = dev->chip_info;
-	/* Find the GPIO bar */
-	res = find_resource(dev, GPIO_BASE);
-	if (!res) {
-		return;
-	}
-
-	/* Set the use selects */
-	set_i82801ex_gpio_use_sel(dev, res, config);
-
-	/* Set the IO direction */
-	set_i82801ex_gpio_direction(dev, res, config);
-
-	/* Setup the input inverters */
-	set_i82801ex_gpio_inv(dev, res, config);
-
-	/* Set the value on the GPIO output pins */
-	set_i82801ex_gpio_level(dev, res, config);
-
-}
-
-static void enable_hpet(struct device *dev)
-{
-	const unsigned long hpet_address = 0xfed00000;
-
-	uint32_t dword;
-	uint32_t code = (0 & 0x3);
-
-	dword = pci_read_config32(dev, GEN_CNTL);
-	dword |= (1 << 17); /* enable hpet */
-
-	/* Bits [16:15]  Memory Address Range
-	 *	    00   FED0_0000h - FED0_03FFh
-	 *	    01   FED0_1000h - FED0_13FFh
-	 *	    10   FED0_2000h - FED0_23FFh
-	 *	    11   FED0_3000h - FED0_33FFh
-	 */
-
-	dword &= ~(3 << 15); /* clear it */
-	dword |= (code<<15);
-	pci_write_config32(dev, GEN_CNTL, dword);
-
-	printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address | (code <<12) );
-}
-
-static void lpc_init(struct device *dev)
-{
-	uint8_t byte;
-	int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
-
-	i82801ex_general_cntl(dev);
-
-	/* IO APIC initialization. */
-	setup_ioapic(VIO_APIC_VADDR, 0); // Don't rename IO APIC ID.
-
-	i82801ex_enable_serial_irqs(dev);
-
-	i82801ex_pci_dma_cfg(dev);
-
-	i82801ex_enable_lpc(dev);
-
-	/* Clear SATA to non raid */
-	pci_write_config8(dev, 0xae, 0x00);
-
-	get_option(&pwr_on, "power_on_after_fail");
-	byte = pci_read_config8(dev, 0xa4);
-	byte &= 0xfe;
-	if (!pwr_on) {
-		byte |= 1;
-	}
-	pci_write_config8(dev, 0xa4, byte);
-	printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off");
-
-	/* Set up the PIRQ */
-	i82801ex_pirq_init(dev);
-
-	/* Set the state of the gpio lines */
-	i82801ex_gpio_init(dev);
-
-	/* Initialize the real time clock */
-	cmos_init(0);
-
-	/* Initialize isa dma */
-	isa_dma_init();
-
-	/* Disable IDE (needed when sata is enabled) */
-	pci_write_config8(dev, 0xf2, 0x60);
-
-	enable_hpet(dev);
-}
-
-static void i82801ex_lpc_read_resources(device_t dev)
-{
-	struct resource *res;
-
-	/* Get the normal PCI resources of this device. */
-	pci_dev_read_resources(dev);
-
-	/* Add the ACPI BAR */
-	res = pci_get_resource(dev, PMBASE);
-
-	/* Add the GPIO BAR */
-	res = pci_get_resource(dev, GPIO_BASE);
-
-	/* Add an extra subtractive resource for both memory and I/O. */
-	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->base = 0;
-	res->size = 0x1000;
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
-		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
-	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->base = 0xff800000;
-	res->size = 0x00800000; /* 8 MB for flash */
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
-		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
-	res = new_resource(dev, 3); /* IOAPIC */
-	res->base = IO_APIC_ADDR;
-	res->size = 0x00001000;
-	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-}
-
-static void i82801ex_lpc_enable_resources(device_t dev)
-{
-	/* Enable the normal PCI resources. */
-	pci_dev_enable_resources(dev);
-
-	/* Enable ACPI and GPIO BARs. */
-	i82801ex_enable_acpi(dev);
-}
-
-static struct pci_operations lops_pci = {
-	.set_subsystem = 0,
-};
-
-static struct device_operations lpc_ops  = {
-	.read_resources   = i82801ex_lpc_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = i82801ex_lpc_enable_resources,
-	.init             = lpc_init,
-	.scan_bus         = scan_lpc_bus,
-	.enable           = i82801ex_enable,
-	.ops_pci          = &lops_pci,
-};
-
-static const struct pci_driver lpc_driver __pci_driver = {
-	.ops    = &lpc_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801ER_LPC,
-};
diff --git a/src/southbridge/intel/i82801ex/pci.c b/src/southbridge/intel/i82801ex/pci.c
deleted file mode 100644
index f1c8183351..0000000000
--- a/src/southbridge/intel/i82801ex/pci.c
+++ /dev/null
@@ -1,44 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "i82801ex.h"
-
-static void pci_init(struct device *dev)
-{
-	uint16_t word;
-
-	/* Clear system errors */
-	word = pci_read_config16(dev, 0x06);
-	word |= 0xf900; /* Clear possible errors */
-	pci_write_config16(dev, 0x06, word);
-
-#if 0
-	/* System error enable */
-	uint32_t dword;
-	dword = pci_read_config32(dev, 0x04);
-	dword |= (1<<8); /* SERR# Enable */
-	dword |= (1<<6); /* Parity Error Response */
-	pci_write_config32(dev, 0x04, dword);
-#endif
-
-	word = pci_read_config16(dev, 0x1e);
-	word |= 0xf800; /* Clear possible errors */
-	pci_write_config16(dev, 0x1e, word);
-}
-
-static struct device_operations pci_ops  = {
-	.read_resources   = pci_bus_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_bus_enable_resources,
-	.init             = pci_init,
-	.scan_bus         = pci_scan_bridge,
-	.ops_pci          = 0,
-};
-
-static const struct pci_driver pci_driver __pci_driver = {
-	.ops    = &pci_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801ER_PCI,
-};
diff --git a/src/southbridge/intel/i82801ex/reset.c b/src/southbridge/intel/i82801ex/reset.c
deleted file mode 100644
index 8036ffde17..0000000000
--- a/src/southbridge/intel/i82801ex/reset.c
+++ /dev/null
@@ -1,8 +0,0 @@
-#include <arch/io.h>
-#include <reset.h>
-
-void hard_reset(void)
-{
-	/* Try rebooting through port 0xcf9 */
-	outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
-}
diff --git a/src/southbridge/intel/i82801ex/sata.c b/src/southbridge/intel/i82801ex/sata.c
deleted file mode 100644
index b3d8f37a94..0000000000
--- a/src/southbridge/intel/i82801ex/sata.c
+++ /dev/null
@@ -1,59 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "i82801ex.h"
-
-static void sata_init(struct device *dev)
-{
-  	printk(BIOS_DEBUG, "SATA init\n");
-	/* SATA configuration */
-	pci_write_config8(dev, 0x04, 0x07);
-	pci_write_config8(dev, 0x09, 0x8f);
-
-	/* Set timmings */
-	pci_write_config16(dev, 0x40, 0x0a307);
-	pci_write_config16(dev, 0x42, 0x0a307);
-
-	/* Sync DMA */
-	pci_write_config16(dev, 0x48, 0x000f);
-	pci_write_config16(dev, 0x4a, 0x1111);
-
-	/* 66 mhz */
-	pci_write_config16(dev, 0x54, 0xf00f);
-
-	/* Combine ide - sata configuration */
-	pci_write_config8(dev, 0x90, 0x0);
-
-	/* port 0 & 1 enable */
-	pci_write_config8(dev, 0x92, 0x33);
-
-	/* initialize SATA  */
-	pci_write_config16(dev, 0xa0, 0x0018);
-	pci_write_config32(dev, 0xa4, 0x00000264);
-	pci_write_config16(dev, 0xa0, 0x0040);
-	pci_write_config32(dev, 0xa4, 0x00220043);
-
-}
-
-static struct device_operations sata_ops  = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = sata_init,
-	.scan_bus         = 0,
-	.ops_pci          = 0,
-};
-
-static const struct pci_driver sata_driver __pci_driver = {
-	.ops    = &sata_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801ER_SATA,
-};
-
-static const struct pci_driver sata_driver_nr __pci_driver = {
-	.ops    = &sata_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801EB_SATA,
-};
diff --git a/src/southbridge/intel/i82801ex/smbus.c b/src/southbridge/intel/i82801ex/smbus.c
deleted file mode 100644
index 75ea1198c1..0000000000
--- a/src/southbridge/intel/i82801ex/smbus.c
+++ /dev/null
@@ -1,48 +0,0 @@
-#include <device/device.h>
-#include <device/path.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <device/smbus.h>
-#include <arch/io.h>
-#include "i82801ex.h"
-#include "smbus.h"
-
-static int lsmbus_read_byte(device_t dev, u8 address)
-{
-	u16 device;
-	struct resource *res;
-	struct bus *pbus;
-
-	device = dev->path.i2c.device;
-	pbus = get_pbus_smbus(dev);
-	res = find_resource(pbus->dev, 0x20);
-
-	return do_smbus_read_byte(res->base, device, address);
-}
-
-static struct smbus_bus_operations lops_smbus_bus = {
-	.read_byte  = lsmbus_read_byte,
-};
-
-static struct pci_operations lops_pci = {
-	/* The subsystem id follows the ide controller */
-	.set_subsystem = 0,
-};
-
-static struct device_operations smbus_ops = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = 0,
-	.scan_bus         = scan_smbus,
-	.enable           = i82801ex_enable,
-	.ops_pci          = &lops_pci,
-	.ops_smbus_bus    = &lops_smbus_bus,
-};
-
-static const struct pci_driver smbus_driver __pci_driver = {
-	.ops    = &smbus_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801ER_SMB,
-};
diff --git a/src/southbridge/intel/i82801ex/smbus.h b/src/southbridge/intel/i82801ex/smbus.h
deleted file mode 100644
index dbb7b7a416..0000000000
--- a/src/southbridge/intel/i82801ex/smbus.h
+++ /dev/null
@@ -1,104 +0,0 @@
-#include <device/smbus_def.h>
-
-#define SMBHSTSTAT 0x0
-#define SMBHSTCTL  0x2
-#define SMBHSTCMD  0x3
-#define SMBXMITADD 0x4
-#define SMBHSTDAT0 0x5
-#define SMBHSTDAT1 0x6
-#define SMBBLKDAT  0x7
-#define SMBTRNSADD 0x9
-#define SMBSLVDATA 0xa
-#define SMLINK_PIN_CTL 0xe
-#define SMBUS_PIN_CTL  0xf
-
-#define SMBUS_TIMEOUT (100*1000*10)
-
-
-static void smbus_delay(void)
-{
-	outb(0x80, 0x80);
-}
-
-static int smbus_wait_until_ready(unsigned smbus_io_base)
-{
-	unsigned loops = SMBUS_TIMEOUT;
-	unsigned char byte;
-	do {
-		smbus_delay();
-		if (--loops == 0)
-			break;
-		byte = inb(smbus_io_base + SMBHSTSTAT);
-	} while (byte & 1);
-	return loops?0:-1;
-}
-
-static int smbus_wait_until_done(unsigned smbus_io_base)
-{
-	unsigned loops = SMBUS_TIMEOUT;
-	unsigned char byte;
-	do {
-	        smbus_delay();
-	        if (--loops == 0)
-	               break;
-	        byte = inb(smbus_io_base + SMBHSTSTAT);
-	} while ((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0);
-	return loops?0:-1;
-}
-
-static inline int smbus_wait_until_blk_done(unsigned smbus_io_base)
-{
-	unsigned loops = SMBUS_TIMEOUT;
-	unsigned char byte;
-	do {
-	        smbus_delay();
-	        if (--loops == 0)
-	               break;
-	        byte = inb(smbus_io_base + SMBHSTSTAT);
-	} while ((byte&(1<<7)) == 0);
-	return loops?0:-1;
-}
-
-static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
-{
-	unsigned char global_status_register;
-	unsigned char byte;
-
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
-	}
-	/* setup transaction */
-	/* disable interrupts */
-	outb(inb(smbus_io_base + SMBHSTCTL) & (~1), smbus_io_base + SMBHSTCTL);
-	/* set the device I'm talking too */
-	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
-	/* set the command/address... */
-	outb(address & 0xFF, smbus_io_base + SMBHSTCMD);
-	/* set up for a byte data read */
-	outb((inb(smbus_io_base + SMBHSTCTL) & 0xE3) | (0x2 << 2), smbus_io_base + SMBHSTCTL);
-	/* clear any lingering errors, so the transaction will run */
-	outb(inb(smbus_io_base + SMBHSTSTAT), smbus_io_base + SMBHSTSTAT);
-
-	/* clear the data byte...*/
-	outb(0, smbus_io_base + SMBHSTDAT0);
-
-	/* start the command */
-	outb((inb(smbus_io_base + SMBHSTCTL) | 0x40), smbus_io_base + SMBHSTCTL);
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
-		return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
-	}
-
-	global_status_register = inb(smbus_io_base + SMBHSTSTAT);
-
-	/* Ignore the In Use Status... */
-	global_status_register &= ~(3 << 5);
-
-	/* read results of transaction */
-	byte = inb(smbus_io_base + SMBHSTDAT0);
-	if (global_status_register != (1 << 1)) {
-		return SMBUS_ERROR;
-	}
-	return byte;
-}
diff --git a/src/southbridge/intel/i82801ex/uhci.c b/src/southbridge/intel/i82801ex/uhci.c
deleted file mode 100644
index c9cf82e686..0000000000
--- a/src/southbridge/intel/i82801ex/uhci.c
+++ /dev/null
@@ -1,55 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "i82801ex.h"
-
-static void uhci_init(struct device *dev)
-{
-	uint32_t cmd;
-
-#if 1
-	printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
-	cmd = pci_read_config32(dev, PCI_COMMAND);
-	pci_write_config32(dev, PCI_COMMAND,
-		cmd | PCI_COMMAND_MASTER);
-
-
-	printk(BIOS_DEBUG, "done.\n");
-#endif
-
-}
-
-static struct pci_operations lops_pci = {
-	/* The subsystem id follows the ide controller */
-	.set_subsystem = 0,
-};
-
-static struct device_operations uhci_ops  = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = uhci_init,
-	.scan_bus         = 0,
-	.enable           = i82801ex_enable,
-	.ops_pci          = &lops_pci,
-};
-
-static const struct pci_driver uhci_driver __pci_driver = {
-	.ops    = &uhci_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801ER_USB1,
-};
-
-static const struct pci_driver usb2_driver __pci_driver = {
-	.ops    = &uhci_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801ER_USB2,
-};
-
-static const struct pci_driver usb3_driver __pci_driver = {
-	.ops    = &uhci_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801ER_USB3,
-};
diff --git a/src/southbridge/intel/i82801ex/watchdog.c b/src/southbridge/intel/i82801ex/watchdog.c
deleted file mode 100644
index 6aba2703cb..0000000000
--- a/src/southbridge/intel/i82801ex/watchdog.c
+++ /dev/null
@@ -1,28 +0,0 @@
-#include <console/console.h>
-#include <watchdog.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include <device/pci.h>
-
-void watchdog_off(void)
-{
-	device_t dev;
-	unsigned long value,base;
-
-	/* turn off the ICH5 watchdog */
-	dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
-	/* Enable I/O space */
-	value = pci_read_config16(dev, 0x04);
-	value |= (1 << 10);
-	pci_write_config16(dev, 0x04, value);
-	/* Get TCO base */
-	base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
-	/* Disable the watchdog timer */
-	value = inw(base + 0x08);
-	value |= 1 << 11;
-	outw(value, base + 0x08);
-	/* Clear TCO timeout status */
-	outw(0x0008, base + 0x04);
-	outw(0x0002, base + 0x06);
-	printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n");
-}