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| author | Furquan Shaikh <furquan@chromium.org> | 2016-11-20 21:04:00 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-11-22 17:32:09 +0100 |
| commit | c28984d9ea08e7d995ef9fc8064c10ec0c0d9d77 (patch) | |
| tree | c113582c3d2d8fb8d54a4c9a53375340fcc302d5 /src/southbridge/intel | |
| parent | 282c8322791800ee0d732fdaa5eb2cd8f7effd58 (diff) | |
| download | coreboot-c28984d9ea08e7d995ef9fc8064c10ec0c0d9d77.tar.xz | |
spi: Clean up SPI flash driver interface
RW flag was added to spi_slave structure to get around a requirement on
some AMD flash controllers that need to group together all spi volatile
operations (write/erase). This rw flag is not a property or attribute of
the SPI slave or controller. Thus, instead of saving it in spi_slave
structure, clean up the SPI flash driver interface. This allows
chipsets/mainboards (that require volatile operations to be grouped) to
indicate beginning and end of such grouped operations.
New user APIs are added to allow users to perform probe, read, write,
erase, volatile group begin and end operations. Callbacks defined in
spi_flash structure are expected to be used only by the SPI flash
driver. Any chipset that requires grouping of volatile operations can
select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and
define callbacks for chipset_volatile_group_{begin,end}.
spi_claim_bus/spi_release_bus calls have been removed from the SPI flash
chip drivers which end up calling do_spi_flash_cmd since it already has
required calls for claiming and releasing SPI bus before performing a
read/write operation.
BUG=None
BRANCH=None
TEST=Compiles successfully.
Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17462
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/common/spi.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 1ab151b79e..e0414220c6 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -737,7 +737,8 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, } -static int ich_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len) +static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset, + size_t len) { u32 start, end, erase_size; int ret; @@ -750,7 +751,6 @@ static int ich_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len) return -1; } - flash->spi->rw = SPI_WRITE_FLAG; ret = spi_claim_bus(flash->spi); if (ret) { printk(BIOS_ERR, "SF: Unable to claim SPI bus\n"); @@ -801,8 +801,8 @@ static void ich_read_data(uint8_t *data, int len) } } -static int ich_hwseq_read(struct spi_flash *flash, - u32 addr, size_t len, void *buf) +static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len, + void *buf) { uint16_t hsfc; uint16_t timeout = 100 * 60; @@ -869,8 +869,8 @@ static void ich_fill_data(const uint8_t *data, int len) writel_(temp32, cntlr.data + (i - (i % 4))); } -static int ich_hwseq_write(struct spi_flash *flash, - u32 addr, size_t len, const void *buf) +static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, + const void *buf) { uint16_t hsfc; uint16_t timeout = 100 * 60; @@ -934,9 +934,9 @@ static struct spi_flash *spi_flash_hwseq(struct spi_slave *spi) flash->spi = spi; flash->name = "Opaque HW-sequencing"; - flash->write = ich_hwseq_write; - flash->erase = ich_hwseq_erase; - flash->read = ich_hwseq_read; + flash->internal_write = ich_hwseq_write; + flash->internal_erase = ich_hwseq_erase; + flash->internal_read = ich_hwseq_read; ich_hwseq_set_addr (0); switch ((cntlr.hsfs >> 3) & 3) { |