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authorPatrick Georgi <pgeorgi@google.com>2018-11-26 10:42:59 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-11-26 09:56:26 +0000
commitc88828daebc2b2b7ba825bb92f4182d920336ba5 (patch)
tree014ffc08c1b2dc90f5f6d47db4f9ffaeadfa5f6e /src/southbridge/intel
parent327205dc2a7ac1dcd0c19080939c8030b0b9b16c (diff)
downloadcoreboot-c88828daebc2b2b7ba825bb92f4182d920336ba5.tar.xz
sb/intel/common: Fix style issue in spi.c
Change-Id: Ife8f7f164b26bea65a0dcde0cab339a1bb599e38 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/29834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan T <stefan.tauner@gmx.at> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/common/spi.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 9e6109e37b..0592379203 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -345,7 +345,7 @@ void spi_init(void)
cntlr->fpr_max = 5;
if (cntlr->hsfs & HSFS_FDV) {
- writel_ (4, &ich9_spi->fdoc);
+ writel_(4, &ich9_spi->fdoc);
cntlr->flmap0 = readl_(&ich9_spi->fdod);
writel_ (0x1000, &ich9_spi->fdoc);
cntlr->flcomp = readl_(&ich9_spi->fdod);