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authorAaron Durbin <adurbin@chromium.org>2017-09-15 14:59:27 -0600
committerAaron Durbin <adurbin@chromium.org>2017-09-20 23:54:20 +0000
commitcfe7ad1e8f7ed6f3d72db2041bf2051ac88e2a5f (patch)
tree4440a1f19698ac7b86aa16b129c0ead05ddfdd7a /src/southbridge/intel
parentb19e33f05ca43a40babe4f081bf6fb0ff53f5d4f (diff)
downloadcoreboot-cfe7ad1e8f7ed6f3d72db2041bf2051ac88e2a5f.tar.xz
southbridge/intel/lynxpoint: refactor rtc failure checking
In order to prepare for checking RTC failure in the early boot paths move the rtc failure calculation to pmutil.c and add a helper function to determine if failure occurred. BUG=b:63054105 Change-Id: I368c31b9935c0fa9e8a1be416435dd76f44ec1ec Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/lynxpoint/Makefile.inc2
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c14
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h3
-rw-r--r--src/southbridge/intel/lynxpoint/pmutil.c10
4 files changed, 19 insertions, 10 deletions
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index 3ecc6a6cc4..3b1ce5a461 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -49,7 +49,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c pch.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c usb_ehci.c usb_xhci.c
romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c
-romstage-y += reset.c early_spi.c rcba.c
+romstage-y += reset.c early_spi.c rcba.c pmutil.c
ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
romstage-y += lp_gpio.c
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index b43ca329b6..a5c2351323 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -284,18 +284,14 @@ static void pch_power_options(device_t dev)
static void pch_rtc_init(struct device *dev)
{
- u8 reg8;
- int rtc_failed;
+ int rtc_failed = rtc_failure();
- reg8 = pci_read_config8(dev, GEN_PMCON_3);
- rtc_failed = reg8 & RTC_BATTERY_DEAD;
if (rtc_failed) {
- reg8 &= ~RTC_BATTERY_DEAD;
- pci_write_config8(dev, GEN_PMCON_3, reg8);
-#if IS_ENABLED(CONFIG_ELOG)
- elog_add_event(ELOG_TYPE_RTC_RESET);
-#endif
+ if (IS_ENABLED(CONFIG_ELOG))
+ elog_add_event(ELOG_TYPE_RTC_RESET);
+ pci_update_config8(dev, GEN_PMCON_3, ~RTC_BATTERY_DEAD, 0);
}
+
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
cmos_init(rtc_failed);
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 000f5460ef..af9e9542b5 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -172,6 +172,9 @@ void disable_all_gpe(void);
void enable_gpe(u32 mask);
void disable_gpe(u32 mask);
+/* Return non-zero when RTC failure happened. */
+int rtc_failure(void);
+
#if !defined(__PRE_RAM__) && !defined(__SMM__)
#include <device/device.h>
#include <arch/acpi.h>
diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c
index b14c1f7c91..642d5befd0 100644
--- a/src/southbridge/intel/lynxpoint/pmutil.c
+++ b/src/southbridge/intel/lynxpoint/pmutil.c
@@ -553,3 +553,13 @@ void disable_gpe(u32 mask)
gpe0_en &= ~mask;
outl(gpe0_en, get_pmbase() + gpe0_reg);
}
+
+int rtc_failure(void)
+{
+#if defined(__SIMPLE_DEVICE__)
+ device_t dev = PCI_DEV(0, 31, 0);
+#else
+ device_t dev = dev_find_slot(0, PCI_DEVFN(31, 0));
+#endif
+ return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD);
+}