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| author | Patrick Georgi <patrick.georgi@secunet.com> | 2011-11-22 10:28:46 +0100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-03-24 20:39:03 +0100 |
| commit | c07466b287b0aaba0fc73decc60bb75fe919fea1 (patch) | |
| tree | 83357440487fbcc2ddf158a796f181b6b2ac46d3 /src/southbridge/intel | |
| parent | 51615091320a18e39ef2c509ec24e7f80ba71f01 (diff) | |
| download | coreboot-c07466b287b0aaba0fc73decc60bb75fe919fea1.tar.xz | |
i82801gx: Use CMOS variable if available for power-on on power failure
We used a hard coded value for some reason. Don't do that, but use CMOS
instead.
Change-Id: Ib83aa07a3e55bed075150354a060317ebc9d5ba7
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/443
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/i82801gx/smihandler.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 48375e451d..5cc25e7ae2 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -279,12 +279,16 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat u8 reg8; u32 reg32; u8 slp_typ; - /* FIXME: the power state on boot should be read from - * CMOS or even better from GNVS. Right now it's hard - * coded at compile time. - */ u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + // save and recover RTC port values + u8 tmp70, tmp72; + tmp70 = inb(0x70); + tmp72 = inb(0x72); + get_option(&s5pwr, "power_on_after_fail"); + outb(tmp70, 0x70); + outb(tmp72, 0x72); + /* First, disable further SMIs */ reg8 = inb(pmbase + SMI_EN); reg8 &= ~SLP_SMI_EN; |