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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-22 00:30:56 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-24 14:28:33 +0000 |
| commit | 1e1515fc9d26a77c088985a22344f6b32d95026a (patch) | |
| tree | 2ce8a5f6f5e088c38b572f67f2927746e3236aa6 /src/southbridge/intel | |
| parent | 1ba62015184c5e8cb750f4f39de9dd382d869cb8 (diff) | |
| download | coreboot-1e1515fc9d26a77c088985a22344f6b32d95026a.tar.xz | |
sb/intel/*: Delete invalid comment
Looks like these comments were moved without checking them. They are no
longer correct nor useful, so kill them with fire.
Change-Id: I3de04b8c03f7c511376dec922a60958ffc3bf6a3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/i82801gx/early_init.c | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/early_pch.c | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index a913873348..ef48ed857a 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -66,7 +66,6 @@ void i82801gx_early_init(void) enable_smbus(); - /* Setting up Southbridge. In the northbridge code. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); i82801gx_setup_bars(); diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 80b8939c5a..e74fdc5849 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -41,7 +41,6 @@ int pch_is_lp(void) static void pch_enable_bars(void) { - /* Setting up Southbridge. In the northbridge code. */ pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); |