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authorElyes HAOUAS <ehaouas@noos.fr>2020-04-06 09:12:50 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-04-09 14:42:56 +0000
commit25d20d3332d76cbeda8c38a39ba9af2ef762d417 (patch)
treefdd996b2e707f407000895c6d759d46a5c38ac48 /src/southbridge/intel
parent200f02a518600659f0517febc180b27f06533115 (diff)
downloadcoreboot-25d20d3332d76cbeda8c38a39ba9af2ef762d417.tar.xz
sb/{bd82x6x,ibexpeak,lynxpoint}/early_smbus: Use macro
Change-Id: If57d785b92f0f09d9def90b8ac87833321e3cfcf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/bd82x6x/early_smbus.c3
-rw-r--r--src/southbridge/intel/ibexpeak/early_smbus.c3
-rw-r--r--src/southbridge/intel/lynxpoint/early_smbus.c3
3 files changed, 6 insertions, 3 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c
index f3151af200..0275078129 100644
--- a/src/southbridge/intel/bd82x6x/early_smbus.c
+++ b/src/southbridge/intel/bd82x6x/early_smbus.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
+#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <device/smbus_host.h>
@@ -17,7 +18,7 @@ int smbus_enable_iobar(uintptr_t base)
pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
/* Check to make sure we've got the right device. */
- if (pci_read_config16(dev, 0x0) != 0x8086)
+ if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL)
return -1;
/* Set SMBus I/O base. */
diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c
index 0c99a2245f..b87c872012 100644
--- a/src/southbridge/intel/ibexpeak/early_smbus.c
+++ b/src/southbridge/intel/ibexpeak/early_smbus.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
+#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <device/smbus_host.h>
@@ -17,7 +18,7 @@ int smbus_enable_iobar(uintptr_t base)
pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
/* Check to make sure we've got the right device. */
- if (pci_read_config16(dev, 0x0) != 0x8086)
+ if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL)
return -1;
/* Set SMBus I/O base. */
diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c
index f3151af200..0275078129 100644
--- a/src/southbridge/intel/lynxpoint/early_smbus.c
+++ b/src/southbridge/intel/lynxpoint/early_smbus.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
+#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <device/smbus_host.h>
@@ -17,7 +18,7 @@ int smbus_enable_iobar(uintptr_t base)
pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
/* Check to make sure we've got the right device. */
- if (pci_read_config16(dev, 0x0) != 0x8086)
+ if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL)
return -1;
/* Set SMBus I/O base. */