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authorAaron Durbin <adurbin@chromium.org>2012-10-31 23:05:25 -0500
committerRonald G. Minnich <rminnich@gmail.com>2013-03-14 06:35:48 +0100
commit89f79a019fd049f26ed7bf40618ff960bd9e095e (patch)
treee3bf2a39fe6f4d9f2570a4373376aeefbf7a3664 /src/southbridge/intel
parentb9ea8b3fb0082840b0c9d449535f4c49c2e885ac (diff)
downloadcoreboot-89f79a019fd049f26ed7bf40618ff960bd9e095e.tar.xz
haswell: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove the pcie explicit accesses. The default config accesses use MMIO. Change-Id: I8406cec16c1ee1bc205b657a0c90beb2252df061 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2618 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/lynxpoint/finalize.c9
-rw-r--r--src/southbridge/intel/lynxpoint/me_9.x.c9
-rw-r--r--src/southbridge/intel/lynxpoint/smihandler.c15
-rw-r--r--src/southbridge/intel/lynxpoint/spi.c13
4 files changed, 21 insertions, 25 deletions
diff --git a/src/southbridge/intel/lynxpoint/finalize.c b/src/southbridge/intel/lynxpoint/finalize.c
index 796633d024..2cece13e17 100644
--- a/src/southbridge/intel/lynxpoint/finalize.c
+++ b/src/southbridge/intel/lynxpoint/finalize.c
@@ -21,7 +21,6 @@
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <console/post_codes.h>
-#include <northbridge/intel/haswell/pcie_config.c>
#include <spi-generic.h>
#include "pch.h"
@@ -51,15 +50,15 @@ void intel_pch_finalize_smm(void)
RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));
/* Global SMI Lock */
- pcie_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);
+ pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);
/* GEN_PMCON Lock */
- pcie_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
+ pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
/* R/WO registers */
RCBA32(0x21a4) = RCBA32(0x21a4);
- pcie_write_config32(PCI_DEV(0, 27, 0), 0x74,
- pcie_read_config32(PCI_DEV(0, 27, 0), 0x74));
+ pci_write_config32(PCI_DEV(0, 27, 0), 0x74,
+ pci_read_config32(PCI_DEV(0, 27, 0), 0x74));
/* Indicate finalize step with post code */
outb(POST_OS_BOOT, 0x80);
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index facfc37645..12f7ab7ed2 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -39,7 +39,6 @@
#ifdef __SMM__
# include <arch/romcc_io.h>
-# include <northbridge/intel/haswell/pcie_config.c>
#else
# include <device/device.h>
# include <device/pci.h>
@@ -496,14 +495,14 @@ void intel_me_finalize_smm(void)
u32 reg32;
mei_base_address =
- pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
+ pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
/* S3 path will have hidden this device already */
if (!mei_base_address || mei_base_address == 0xfffffff0)
return;
/* Make sure ME is in a mode that expects EOP */
- reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS);
+ reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
memcpy(&hfs, &reg32, sizeof(u32));
/* Abort and leave device alone if not normal mode */
@@ -516,10 +515,10 @@ void intel_me_finalize_smm(void)
mkhi_end_of_post();
/* Make sure IO is disabled */
- reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND);
+ reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
- pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
+ pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
/* Hide the PCI device */
RCBA32_OR(FD2, PCH_DISABLE_MEI1);
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index c5c2c3ec15..d31e350b76 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -38,7 +38,6 @@
* 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
*/
#include <northbridge/intel/haswell/haswell.h>
-#include <northbridge/intel/haswell/pcie_config.c>
/* While we read PMBASE dynamically in case it changed, let's
* initialize it with a sane value
@@ -65,7 +64,7 @@ static u32 tseg_base = 0;
u32 smi_get_tseg_base(void)
{
if (!tseg_base)
- tseg_base = pcie_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1;
+ tseg_base = pci_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1;
return tseg_base;
}
void tseg_relocate(void **ptr)
@@ -302,7 +301,7 @@ static void southbridge_gate_memory_reset(void)
u32 reg32;
u16 gpiobase;
- gpiobase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
+ gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
if (!gpiobase)
return;
@@ -388,13 +387,13 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
/* Always set the flag in case CMOS was changed on runtime. For
* "KEEP", switch to "OFF" - KEEP is software emulated
*/
- reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
if (s5pwr == MAINBOARD_POWER_ON) {
reg8 &= ~1;
} else {
reg8 |= 1;
}
- pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
/* also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);
@@ -625,7 +624,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_
if (tco_sts & (1 << 8)) { // BIOSWR
u8 bios_cntl;
- bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
+ bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
if (bios_cntl & 1) {
/* BWE is RW, so the SMI was caused by a
@@ -639,7 +638,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_
* box.
*/
printk(BIOS_DEBUG, "Switching back to RO\n");
- pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
} /* No else for now? */
} else if (tco_sts & (1 << 3)) { /* TIMEOUT */
/* Handle TCO timeout */
@@ -766,7 +765,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
u32 smi_sts;
/* Update global variable pmbase */
- pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+ pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
/* We need to clear the SMI status registers, or we won't see what's
* happening in the following calls.
diff --git a/src/southbridge/intel/lynxpoint/spi.c b/src/southbridge/intel/lynxpoint/spi.c
index 8eea28c88f..ec7c862beb 100644
--- a/src/southbridge/intel/lynxpoint/spi.c
+++ b/src/southbridge/intel/lynxpoint/spi.c
@@ -35,19 +35,18 @@
#ifdef __SMM__
#include <arch/romcc_io.h>
-#include <northbridge/intel/haswell/pcie_config.c>
#define pci_read_config_byte(dev, reg, targ)\
- *(targ) = pcie_read_config8(dev, reg)
+ *(targ) = pci_read_config8(dev, reg)
#define pci_read_config_word(dev, reg, targ)\
- *(targ) = pcie_read_config16(dev, reg)
+ *(targ) = pci_read_config16(dev, reg)
#define pci_read_config_dword(dev, reg, targ)\
- *(targ) = pcie_read_config32(dev, reg)
+ *(targ) = pci_read_config32(dev, reg)
#define pci_write_config_byte(dev, reg, val)\
- pcie_write_config8(dev, reg, val)
+ pci_write_config8(dev, reg, val)
#define pci_write_config_word(dev, reg, val)\
- pcie_write_config16(dev, reg, val)
+ pci_write_config16(dev, reg, val)
#define pci_write_config_dword(dev, reg, val)\
- pcie_write_config32(dev, reg, val)
+ pci_write_config32(dev, reg, val)
#else /* !__SMM__ */
#include <device/device.h>
#include <device/pci.h>