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authorAaron Durbin <adurbin@chromium.org>2015-09-23 19:54:12 -0500
committerAaron Durbin <adurbin@chromium.org>2015-09-24 16:12:44 +0000
commit9796f60c62f57ac512f225809c10b5b09ef80f5a (patch)
tree5d6c3e1d933782bbb03af4ac7a21579f722b5327 /src/southbridge/intel
parenta40032780fe4da7d95b203fb3d05a25183590952 (diff)
downloadcoreboot-9796f60c62f57ac512f225809c10b5b09ef80f5a.tar.xz
coreboot: move TS_END_ROMSTAGE to one spot
While the romstage code flow is not consistent across all mainboards/chipsets there is only one way of running ramstage from romstage -- run_ramstage(). Move the timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage(). BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. TS_END_ROMSTAGE still present in timestamp table. Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11700 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/fsp_rangeley/romstage.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index 3500dfd6e6..bc58b487c0 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -130,8 +130,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
*(u32*)cbmem_hob_ptr = (u32)hob_list_ptr;
post_code(0x4e);
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_code(0x4f);
/* Load the ramstage. */