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authorArthur Heymans <arthur@aheymans.xyz>2019-01-15 20:14:33 +0100
committerArthur Heymans <arthur@aheymans.xyz>2019-05-25 15:49:27 +0000
commit99e578e3c1697028957f25efc7c14d1cb4d405dc (patch)
tree44853df46744994d5caf3172a579f9d92252155b /src/southbridge/intel
parentc752c500fbcc055e8cdfb30a2e523e8a9349b79f (diff)
downloadcoreboot-99e578e3c1697028957f25efc7c14d1cb4d405dc.tar.xz
nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK
This adds a file i82801gx/bootblock_gcc.c since other targets that don't yet C_ENVIRONMENT_BOOTBLOCK still use the romcc compiled bootblock.c. Tested on Foxconn D41S. Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/i82801gx/Makefile.inc2
-rw-r--r--src/southbridge/intel/i82801gx/bootblock_gcc.c44
2 files changed, 46 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc
index 32a4bf5333..6e7f9bf945 100644
--- a/src/southbridge/intel/i82801gx/Makefile.inc
+++ b/src/southbridge/intel/i82801gx/Makefile.inc
@@ -15,6 +15,8 @@
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y)
+bootblock-y += bootblock_gcc.c
+
ramstage-y += i82801gx.c
ramstage-y += ac97.c
ramstage-y += azalia.c
diff --git a/src/southbridge/intel/i82801gx/bootblock_gcc.c b/src/southbridge/intel/i82801gx/bootblock_gcc.c
new file mode 100644
index 0000000000..996788888a
--- /dev/null
+++ b/src/southbridge/intel/i82801gx/bootblock_gcc.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/pci_ops.h>
+#include <cpu/intel/car/bootblock.h>
+#include "i82801gx.h"
+
+static void enable_spi_prefetch(void)
+{
+ u8 reg8;
+ pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
+
+ reg8 = pci_read_config8(dev, BIOS_CNTL);
+ reg8 &= ~(3 << 2);
+ reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+ pci_write_config8(dev, BIOS_CNTL, reg8);
+}
+
+void bootblock_early_southbridge_init(void)
+{
+ enable_spi_prefetch();
+
+ /* Enable RCBA */
+ pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0);
+ pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
+
+ /* Enable upper 128bytes of CMOS */
+ RCBA32(0x3400) = (1 << 2);
+
+ /* Disable watchdog timer */
+ RCBA32(GCS) = RCBA32(GCS) | 0x20;
+}