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authorAaron Durbin <adurbin@chromium.org>2013-03-27 20:57:28 -0500
committerRonald G. Minnich <rminnich@gmail.com>2013-04-01 23:24:32 +0200
commitaf3158c0cfd6034bbdc42a0488382c4be1a7a388 (patch)
treea8012866f1715552dedb68f3ee727366fb4fc0c3 /src/southbridge/intel
parent9ebd8ea7cfd379cca56a2c48324bdfbe52ff6bab (diff)
downloadcoreboot-af3158c0cfd6034bbdc42a0488382c4be1a7a388.tar.xz
lynxpoint: split clearing and enabling of smm
Previously southbridge_smm_init() was provided that did both the clearing of the SMM state and enabling SMIs. This is troublesome in how haswell machines bring up the APs. The BSP enters SMM once to determine if parallel SMM relocation is possible. If it is possible the BSP releases the APs to do SMM relocation. Normally, after the APs complete the SMM relocation, the BSP would then re-enter the relocation handler to relocate its own SMM space. However, because SMIs were previously enabled it is possible for an SMI event to occur before the APs are complete or have entered the relocation handler. This is bad because the BSP will turn off parallel SMM save state. Additionally, this is a problem because the relocation handler is not written to handle regular SMIs which can cause an SMI storm which effectively looks like a hung machine. Correct these issues by turning on SMIs after all the SMM relocation has occurred. Change-Id: Id4f07553b110b9664d51d2e670a14e6617591500 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2977 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h6
-rw-r--r--src/southbridge/intel/lynxpoint/smi.c6
2 files changed, 10 insertions, 2 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index ee2efd55bd..3535b987ce 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -170,9 +170,13 @@ void pch_log_state(void);
void acpi_create_intel_hpet(acpi_hpet_t * hpet);
/* These helpers are for performing SMM relocation. */
-void southbridge_smm_init(void);
void southbridge_trigger_smi(void);
void southbridge_clear_smi_status(void);
+/* The initialization of the southbridge is split into 2 compoments. One is
+ * for clearing the state in the SMM registers. The other is for enabling
+ * SMIs. They are split so that other work between the 2 actions. */
+void southbridge_smm_clear_state(void);
+void southbridge_smm_enable_smi(void);
#else
void enable_smbus(void);
void enable_usb_bar(void);
diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c
index 176d400256..75c3e66743 100644
--- a/src/southbridge/intel/lynxpoint/smi.c
+++ b/src/southbridge/intel/lynxpoint/smi.c
@@ -30,7 +30,7 @@
#include <string.h>
#include "pch.h"
-void southbridge_smm_init(void)
+void southbridge_smm_clear_state(void)
{
u32 smi_en;
@@ -54,7 +54,11 @@ void southbridge_smm_init(void)
clear_pm1_status();
clear_tco_status();
clear_gpe_status();
+}
+void southbridge_smm_enable_smi(void)
+{
+ printk(BIOS_DEBUG, "Enabling SMIs.\n");
/* Configure events */
enable_pm1(PWRBTN_EN | GBL_EN);
disable_gpe(PME_B0_EN);