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authorArthur Heymans <arthur@aheymans.xyz>2019-10-12 14:35:25 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-10-28 11:59:17 +0000
commitbe9533aba957e9c43f77381f436906951c13c98b (patch)
treeb4ad42a54424f29043ce91b7d5135e6de2cad6f1 /src/southbridge/intel
parent942ad6a137027d6a7d8d082dee20bb64c81dc813 (diff)
downloadcoreboot-be9533aba957e9c43f77381f436906951c13c98b.tar.xz
nb/intel/gm45: Add C_ENVIRONMENT_BOOTBLOCK support
The i82801ix_early_init is now called both in the bootblock and romstage. The rationale behind setting this up twice is to ensure bootblock-romstage compatibility in the future if for instance VBOOT is used. This moves the console init to the bootblock. The romstage now runs uncached. Adding a prog_run hooks to set up an MTRR to cache the romstage will be done in a followup patch. The default size of 64KiB is not modified for the bootblock as trying to fit both EHCI and SPI flash debugging needs a more space and 64KiB is the next power of 2 size that fits it. TESTED on Thinkpad X200. Change-Id: I8f59736cb54377973215f35e35d2cbcd1d82c374 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/i82801ix/Kconfig4
-rw-r--r--src/southbridge/intel/i82801ix/Makefile.inc3
-rw-r--r--src/southbridge/intel/i82801ix/bootblock.c8
3 files changed, 10 insertions, 5 deletions
diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig
index 5edb8a1426..5e9f513b78 100644
--- a/src/southbridge/intel/i82801ix/Kconfig
+++ b/src/southbridge/intel/i82801ix/Kconfig
@@ -47,8 +47,4 @@ config HPET_MIN_TICKS
hex
default 0x80
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "southbridge/intel/i82801ix/bootblock.c"
-
endif
diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc
index 49db1230b7..41d1b89430 100644
--- a/src/southbridge/intel/i82801ix/Makefile.inc
+++ b/src/southbridge/intel/i82801ix/Makefile.inc
@@ -35,6 +35,9 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S
endif
smm-y += smihandler.c
+bootblock-y += bootblock.c
+bootblock-y += early_init.c
+
romstage-y += early_init.c
romstage-y += early_smbus.c
romstage-y += dmi_setup.c
diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c
index 1957512cc0..0b50d61fba 100644
--- a/src/southbridge/intel/i82801ix/bootblock.c
+++ b/src/southbridge/intel/i82801ix/bootblock.c
@@ -14,6 +14,9 @@
*/
#include <device/pci_ops.h>
+#include <cpu/intel/car/bootblock.h>
+#include "i82801ix.h"
+
static void enable_spi_prefetch(void)
{
@@ -28,7 +31,10 @@ static void enable_spi_prefetch(void)
pci_write_config8(dev, 0xdc, reg8);
}
-static void bootblock_southbridge_init(void)
+void bootblock_early_southbridge_init(void)
{
enable_spi_prefetch();
+
+ i82801ix_early_init();
+ i82801ix_lpc_decode();
}