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authorArthur Heymans <arthur@aheymans.xyz>2018-04-10 15:16:48 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-01-23 14:47:53 +0000
commitc82950bf79285fa838b6fbaf019a5638316ba053 (patch)
tree3f344f1d85367986ee0e635b724d9e6ff3a23589 /src/southbridge/intel
parentf26693283655eff7c31275621439f8416eeb3242 (diff)
downloadcoreboot-c82950bf79285fa838b6fbaf019a5638316ba053.tar.xz
nb/intel/x4x: Use parallel MP init
Use parallel MP init code to initialize all AP's. Also remove guards around CPU code where all platforms now use parallel MP init. This also removes the code required on lapic init path for model_6fx, model_1017x and model_f4x as all platforms now use the parallel MP code. Tested on Intel DG41WV, shaves off about 90ms on a quad core. Change-Id: Id5a2729f5bf6b525abad577e63d7953ae6640921 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25601 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/i82801jx/lpc.c4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c
index 3f7095cbdc..b06959aa5b 100644
--- a/src/southbridge/intel/i82801jx/lpc.c
+++ b/src/southbridge/intel/i82801jx/lpc.c
@@ -392,10 +392,6 @@ static void i82801jx_lock_smm(struct device *dev)
printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT);
}
- /* Don't allow evil boot loaders, kernels, or
- * userspace applications to deceive us:
- */
- smm_lock();
#if TEST_SMM_FLASH_LOCKDOWN
/* Now try this: */