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authorMartin Roth <martinroth@google.com>2015-11-12 14:02:42 -0700
committerMartin Roth <martinroth@google.com>2015-11-19 00:16:50 +0100
commit1455437c9e010bcc617c5927e18cf1cb3b02c82f (patch)
tree090b6d94cdd166d4302aa0053c8d37cfb19de642 /src/southbridge/intel
parentae16c4034c37a28e352936d0600b51be21340524 (diff)
downloadcoreboot-1455437c9e010bcc617c5927e18cf1cb3b02c82f.tar.xz
x86: Add Kconfig to disable early bootblock postcodes
The Intel cave creek chipset needs to have port 80 routing configured before any post codes can be sent to port 80h. Sending post codes out before the routing is done will hang the system. This patch allows us to disable the first couple of post codes that go out before the routing can be configured. The Kconfig symbol is selected by the cave creek chipset (fsp_i89xx). Change-Id: I9bf41669ec32744f87a1ed2de011d31c72ea38da Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12422 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: York Yang <york.yang@intel.com>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/fsp_i89xx/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/fsp_i89xx/Kconfig b/src/southbridge/intel/fsp_i89xx/Kconfig
index d1426d670b..9d195d2647 100644
--- a/src/southbridge/intel/fsp_i89xx/Kconfig
+++ b/src/southbridge/intel/fsp_i89xx/Kconfig
@@ -34,6 +34,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select SPI_FLASH
select COMMON_FADT
select HAVE_INTEL_FIRMWARE
+ select NO_EARLY_BOOTBLOCK_POSTCODES
config EHCI_BAR
hex