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authorNicolas Reinecke <nr@das-labor.org>2015-04-16 23:25:00 +0200
committerEdward O'Callaghan <edward.ocallaghan@koparo.com>2015-04-20 23:50:38 +0200
commit59aef5c79e7ae85854a88db4803334617d7b83fd (patch)
treeb0a00b163b009e0772b03003bf287ab62e3ffbee /src/southbridge/intel
parentf21b657f27965beacd2a3134aafbf66d4db60930 (diff)
downloadcoreboot-59aef5c79e7ae85854a88db4803334617d7b83fd.tar.xz
southbrige/intel/bd82x6x: add XHCI overcurrent map config
Change-Id: I9a40e5a1028c7674e6dd54742e6646ba48ce7696 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/9449 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/bd82x6x/chip.h2
-rw-r--r--src/southbridge/intel/bd82x6x/pch.h1
-rw-r--r--src/southbridge/intel/bd82x6x/usb_xhci.c3
3 files changed, 6 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index f4be82d81f..f14f4ad3a6 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -94,6 +94,8 @@ struct southbridge_intel_bd82x6x_config {
uint32_t xhci_switchable_ports;
/* Ports which support SuperSpeed (USB 3.0 additional lanes). */
uint32_t superspeed_capable_ports;
+ /* Overcurrent Mapping for USB 3.0 Ports */
+ uint32_t xhci_overcurrent_mapping;
};
#endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 7b52ebc3e3..4ec29035d1 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -449,6 +449,7 @@ early_usb_init (const struct southbridge_usb_port *portmap);
#define USBOCM2 0x35a4 /* 32bit */
/* XHCI USB 3.0 */
+#define XOCM 0xc0 /* 32bit */
#define XUSB2PRM 0xd4 /* 32bit */
#define USB3PRM 0xdc /* 32bit */
diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c
index 3e6ce6b341..639d640d3d 100644
--- a/src/southbridge/intel/bd82x6x/usb_xhci.c
+++ b/src/southbridge/intel/bd82x6x/usb_xhci.c
@@ -33,6 +33,9 @@ static void usb_xhci_init(struct device *dev)
printk(BIOS_DEBUG, "XHCI: Setting up controller.. ");
+ if (config->xhci_overcurrent_mapping)
+ pci_write_config32(dev, XOCM, config->xhci_overcurrent_mapping);
+
/* lock overcurrent map */
reg32 = pci_read_config32(dev, 0x44);
reg32 |= 1;