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authorAlexander Couzens <lynxis@fe80.eu>2015-04-12 22:18:55 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-06-05 21:11:43 +0200
commit5eea458822d394fd65a9b69f0b5b8e33c75065a8 (patch)
tree18a34c6ca29bbc65dd47acefb0786fa2dc044f34 /src/southbridge/intel
parenta90dad1bf08d528407b4a6aee031b5b859c60487 (diff)
downloadcoreboot-5eea458822d394fd65a9b69f0b5b8e33c75065a8.tar.xz
device_ops: add device_t argument to acpi_fill_ssdt_generator
`device_t device` is missing as argument. Every device_op function should have a `device_t device` argument. Change-Id: I7fca8c3fa15c1be672e50e4422d7ac8e4aaa1e36 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/9598 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c2
-rw-r--r--src/southbridge/intel/i82371eb/acpi_tables.c2
-rw-r--r--src/southbridge/intel/i82371eb/isa.c4
-rw-r--r--src/southbridge/intel/i82801ix/lpc.c2
-rw-r--r--src/southbridge/intel/ibexpeak/lpc.c2
5 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 0c24a0aff0..6bf43decef 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -797,7 +797,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_gpe1_blk.addrh = 0x0;
}
-static void southbridge_fill_ssdt(void)
+static void southbridge_fill_ssdt(device_t device)
{
device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
config_t *chip = dev->chip_info;
diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c
index c9192055ff..fa3029c7e5 100644
--- a/src/southbridge/intel/i82371eb/acpi_tables.c
+++ b/src/southbridge/intel/i82371eb/acpi_tables.c
@@ -45,7 +45,7 @@ static int determine_total_number_of_cores(void)
return count;
}
-void generate_cpu_entries(void)
+void generate_cpu_entries(device_t device)
{
int cpu, pcontrol_blk=DEFAULT_PMBASE+PCNTRL, plen=6;
int numcpus = determine_total_number_of_cores();
diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
index 024604b339..61006e672c 100644
--- a/src/southbridge/intel/i82371eb/isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -129,10 +129,10 @@ static void sb_read_resources(struct device *dev)
}
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
-static void southbridge_acpi_fill_ssdt_generator(void)
+static void southbridge_acpi_fill_ssdt_generator(device_t device)
{
acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS");
- generate_cpu_entries();
+ generate_cpu_entries(device);
}
#endif
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 7c11310a88..ac1d49f8e3 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -562,7 +562,7 @@ static void southbridge_inject_dsdt(device_t dev)
}
}
-static void southbridge_fill_ssdt(void)
+static void southbridge_fill_ssdt(device_t device)
{
device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
config_t *chip = dev->chip_info;
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 58a00d56fe..6565293f22 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -784,7 +784,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_gpe1_blk.addrh = 0x0;
}
-static void southbridge_fill_ssdt(void)
+static void southbridge_fill_ssdt(device_t device)
{
device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
config_t *chip = dev->chip_info;