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authorArthur Heymans <arthur@aheymans.xyz>2019-01-03 21:11:45 +0100
committerMartin Roth <martinroth@google.com>2019-04-21 23:32:37 +0000
commit77d5e7481b56ac396e02e73259d1fb414b375470 (patch)
tree5754db12616243655be98cd4fecfa23f86e5e15d /src/southbridge/intel
parent8e646e74b3d5e1d4a5e8114f03046f3d7b6ad042 (diff)
downloadcoreboot-77d5e7481b56ac396e02e73259d1fb414b375470.tar.xz
nb/intel/haswell: Add an option for where verstage starts
Previously Haswell used a romcc bootblock and starting verstage in romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also possible to have a separate verstage. This selects using a separate verstage by default but still keeps the option around to use verstage in romstage. Also make sure mrc.bin is only added to the COREBOOT fmap region as it requires to be run at a specific offset. This means that coreboot will have to jump from a RW region to the RO region for that binary and back to that RW region after that binary is done initializing the memory. Change-Id: I3b7b29f4a24c0fb830ff76fe31a35b6afcae4e67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26926 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/common/Makefile.inc2
-rw-r--r--src/southbridge/intel/lynxpoint/Makefile.inc3
-rw-r--r--src/southbridge/intel/lynxpoint/pmutil.c3
3 files changed, 8 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc
index ac339a2915..1085f6c66a 100644
--- a/src/southbridge/intel/common/Makefile.inc
+++ b/src/southbridge/intel/common/Makefile.inc
@@ -29,6 +29,7 @@ romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB) += pmclib.c
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y)
+verstage-y += pmbase.c
romstage-y += pmbase.c
ramstage-y += pmbase.c
postcar-y += pmbase.c
@@ -59,6 +60,7 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT) += madt.c
smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c
+verstage-y += rtc.c
romstage-y += rtc.c
ramstage-y += rtc.c
postcar-y += rtc.c
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index 62766dfe90..fd00f6c50e 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -55,4 +55,7 @@ ramstage-y += lp_gpio.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += lp_gpio.c
endif
+verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += pmutil.c
+verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += lp_gpio.c
+
endif
diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c
index 3c63723f72..cc494771dd 100644
--- a/src/southbridge/intel/lynxpoint/pmutil.c
+++ b/src/southbridge/intel/lynxpoint/pmutil.c
@@ -24,6 +24,9 @@
#include <device/pci.h>
#include <device/pci_def.h>
#include <console/console.h>
+#include <security/vboot/vbnv.h>
+#include <security/vboot/vboot_common.h>
+#include <southbridge/intel/common/rtc.h>
#include "pch.h"
#if CONFIG(INTEL_LYNXPOINT_LP)