ICH4 update, fix ATA init, drop SATA (chipset doesn't have SATA)

fix some PCI IDs, enable USB bus mastering, add some license headers, ...

LPC code needs another look, but I think we're getting there.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5207 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

17 files changed, 604 insertions, 403 deletions

diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig
index 62da5cf856..0f749b548f 100644
--- a/src/southbridge/intel/i82801dx/Kconfig
+++ b/src/southbridge/intel/i82801dx/Kconfig
@@ -1,3 +1,24 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008-2009 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
 config SOUTHBRIDGE_INTEL_I82801DX
 	bool
 	select IOAPIC
diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc
index 562e80afe0..419ce1c1f3 100644
--- a/src/southbridge/intel/i82801dx/Makefile.inc
+++ b/src/southbridge/intel/i82801dx/Makefile.inc
@@ -1,12 +1,33 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008-2009 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
 driver-y += i82801dx.o
-driver-y += i82801dx_usb.o
-driver-y += i82801dx_lpc.o
-driver-y += i82801dx_ide.o
-driver-y += i82801dx_usb2.o
 driver-y += i82801dx_ac97.o
-#driver-y += i82801dx_nic.o
+driver-y += i82801dx_ide.o
+driver-y += i82801dx_lpc.o
 #driver-y += i82801dx_pci.o
-obj-y += i82801dx_reset.o
+driver-y += i82801dx_usb.o
+driver-y += i82801dx_usb2.o
 
+obj-y += i82801dx_reset.o
 obj-$(CONFIG_HAVE_SMI_HANDLER) += i82801dx_smi.o
+
 smmobj-$(CONFIG_HAVE_SMI_HANDLER) += i82801dx_smihandler.o
diff --git a/src/southbridge/intel/i82801dx/chip.h b/src/southbridge/intel/i82801dx/chip.h
index fdbb7d2d0d..1209ec854b 100644
--- a/src/southbridge/intel/i82801dx/chip.h
+++ b/src/southbridge/intel/i82801dx/chip.h
@@ -1,8 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Eric Biederman
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
 #ifndef I82801DX_CHIP_H
 #define I82801DX_CHIP_H
 
-struct southbridge_intel_i82801dx_config 
-{
+struct southbridge_intel_i82801dx_config {
 	int enable_usb;
 	int enable_native_ide;
 	/**
@@ -24,4 +43,4 @@ struct southbridge_intel_i82801dx_config
 
 extern struct chip_operations southbridge_intel_i82801dx_ops;
 
-#endif /* I82801DBM_CHIP_H */
+#endif				/* I82801DBM_CHIP_H */
diff --git a/src/southbridge/intel/i82801dx/cmos_failover.c b/src/southbridge/intel/i82801dx/cmos_failover.c
index 4821fad3d2..3654a0ae0c 100644
--- a/src/southbridge/intel/i82801dx/cmos_failover.c
+++ b/src/southbridge/intel/i82801dx/cmos_failover.c
@@ -1,16 +1,35 @@
-//kind of cmos_err for ich5
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ron G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+// kind of cmos_err for ICH4
 #define RTC_FAILED    (1 <<2)
 #define GEN_PMCON_3     0xa4
-static void check_cmos_failed(void) 
+static void check_cmos_failed(void)
 {
-
-                uint8_t byte;
-                byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
-                if( byte & RTC_FAILED){
-//clear bit 1 and bit 2
-                        byte = cmos_read(RTC_BOOT_BYTE);
-                        byte &= 0x0c;
-                        byte |= CONFIG_MAX_REBOOT_CNT << 4;
-                        cmos_write(byte, RTC_BOOT_BYTE);
-                }
+	u8 byte;
+	byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
+	if (byte & RTC_FAILED) {
+		//clear bit 1 and bit 2
+		byte = cmos_read(RTC_BOOT_BYTE);
+		byte &= 0x0c;
+		byte |= CONFIG_MAX_REBOOT_CNT << 4;
+		cmos_write(byte, RTC_BOOT_BYTE);
+	}
 }
diff --git a/src/southbridge/intel/i82801dx/i82801dx.c b/src/southbridge/intel/i82801dx/i82801dx.c
index abfd8c21cf..282ccfd247 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.c
+++ b/src/southbridge/intel/i82801dx/i82801dx.c
@@ -1,3 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ron G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -10,48 +30,49 @@ void i82801dx_enable(device_t dev)
 	uint8_t bHasDisableBit = 0;
 	uint16_t cur_disable_mask, new_disable_mask;
 
-//	all 82801dbm devices are in bus 0
-	unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc
-	device_t lpc_dev = dev_find_slot(0, devfn); // 0
+//      all 82801dbm devices are in bus 0
+	unsigned int devfn = PCI_DEVFN(0x1f, 0);	// lpc
+	device_t lpc_dev = dev_find_slot(0, devfn);	// 0
 	if (!lpc_dev)
 		return;
 
 	// Calculate disable bit position for specified device:function
 	// NOTE: For ICH-4, only the following devices can be disabled:
-	//		 D31: F0, F1, F3, F5, F6, 
-	//		 D29: F0, F1, F2, F7
+	//               D31: F0, F1, F3, F5, F6, 
+	//               D29: F0, F1, F2, F7
 
-    if (PCI_SLOT(dev->path.pci.devfn) == 31) {
-    	index = PCI_FUNC(dev->path.pci.devfn);
+	if (PCI_SLOT(dev->path.pci.devfn) == 31) {
+		index = PCI_FUNC(dev->path.pci.devfn);
 
 		switch (index) {
-			case 0:
-			case 1:
-			case 3:
-			case 5:
-			case 6:
-				bHasDisableBit = 1;
-				break;
-			
-			default:
-				break;
+		case 0:
+		case 1:
+		case 3:
+		case 5:
+		case 6:
+			bHasDisableBit = 1;
+			break;
+
+		default:
+			break;
 		};
-		
+
 		if (index == 0)
-			index = 14;		// D31:F0 bit is an exception
+			index = 14;	// D31:F0 bit is an exception
 
-    } else if (PCI_SLOT(dev->path.pci.devfn) == 29) {
-    	index = 8 + PCI_FUNC(dev->path.pci.devfn);
+	} else if (PCI_SLOT(dev->path.pci.devfn) == 29) {
+		index = 8 + PCI_FUNC(dev->path.pci.devfn);
 
-		if ((PCI_FUNC(dev->path.pci.devfn) < 3) || (PCI_FUNC(dev->path.pci.devfn) == 7))
+		if ((PCI_FUNC(dev->path.pci.devfn) < 3)
+		    || (PCI_FUNC(dev->path.pci.devfn) == 7))
 			bHasDisableBit = 1;
-    }
+	}
 
 	if (bHasDisableBit) {
 		cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);
-		new_disable_mask = cur_disable_mask & ~(1<<index); 		// enable it
+		new_disable_mask = cur_disable_mask & ~(1 << index);	// enable it
 		if (!dev->enabled) {
-			new_disable_mask |= (1<<index);  // disable it
+			new_disable_mask |= (1 << index);	// disable it
 		}
 		if (new_disable_mask != cur_disable_mask) {
 			pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask);
@@ -61,5 +82,5 @@ void i82801dx_enable(device_t dev)
 
 struct chip_operations southbridge_intel_i82801dx_ops = {
 	CHIP_NAME("Intel ICH4/ICH4-M (82801Dx) Series Southbridge")
-	.enable_dev = i82801dx_enable,
+	    .enable_dev = i82801dx_enable,
 };
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h
index d4e1aa0928..04092966bc 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.h
+++ b/src/southbridge/intel/i82801dx/i82801dx.h
@@ -1,3 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ron G. Minnich
+ * Copyright (C) 2004 Eric Biederman
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
 /* the problem: we have 82801dbm support in fb1, and 82801er in fb2. 
  * fb1 code is what we want, fb2 structure is needed however. 
  * so we need to get fb1 code for 82801dbm into fb2 structure. 
@@ -23,15 +45,23 @@ extern void i82801dx_enable(device_t dev);
 #endif
 
 /*
-000 = Non-combined. P0 is primary master. P1 is secondary master.
-001 = Non-combined. P0 is secondary master. P1 is primary master.
-100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary; Primary IDE channel
-disabled.
-101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary.
-110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary slave; Secondary IDE
-channel disabled.
-111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master.
-*/
+ * 000 = Non-combined. P0 is primary master. P1 is secondary master.
+ * 001 = Non-combined. P0 is secondary master. P1 is primary master.
+ * 100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary;
+ *       Primary IDE channel disabled.
+ * 101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary.
+ * 110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary
+ *       slave; Secondary IDE channel disabled.
+ * 111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master.
+ */
+/* PCI Configuration Space (D31:F1) */
+#define IDE_TIM_PRI		0x40	/* IDE timings, primary */
+#define IDE_TIM_SEC		0x42	/* IDE timings, secondary */
+
+/* IDE_TIM bits */
+#define IDE_DECODE_ENABLE	(1 << 15)
+
+
 
 #define PCI_DMA_CFG     0x90
 #define SERIRQ_CNTL     0x64
diff --git a/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c b/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c
index 0a0ff91f34..30d197c461 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c
@@ -1,3 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
 
 //#define SMBUS_IO_BASE 0x1000
 //#define SMBUS_IO_BASE 0x0f00
@@ -12,7 +31,7 @@
 #define SMBTRNSADD 0x9
 #define SMBSLVDATA 0xa
 #define SMLINK_PIN_CTL 0xe
-#define SMBUS_PIN_CTL  0xf 
+#define SMBUS_PIN_CTL  0xf
 
 /* Between 1-10 seconds, We should never timeout normally 
  * Longer than this is just painful when a timeout condition occurs.
@@ -28,15 +47,14 @@ static void enable_smbus(void)
 	pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
 	/* Set smbus enable */
 	pci_write_config8(dev, 0x40, 0x01);
-	/* Set smbus iospace enable */ 
+	/* Set smbus iospace enable */
 	pci_write_config16(dev, 0x4, 0x01);
-	/* Disable interrupt generation */ 
+	/* Disable interrupt generation */
 	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
 	/* clear any lingering errors, so the transaction will run */
 	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
 }
 
-
 static inline void smbus_delay(void)
 {
 	outb(0x80, 0x80);
@@ -53,8 +71,8 @@ static int smbus_wait_until_active(void)
 		if ((val & 1)) {
 			break;
 		}
-	} while(--loops);
-	return loops?0:-4;
+	} while (--loops);
+	return loops ? 0 : -4;
 }
 
 static int smbus_wait_until_ready(void)
@@ -68,12 +86,12 @@ static int smbus_wait_until_ready(void)
 		if ((val & 1) == 0) {
 			break;
 		}
-		if(loops == (SMBUS_TIMEOUT / 2)) {
-			outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), 
-				SMBUS_IO_BASE + SMBHSTSTAT);
+		if (loops == (SMBUS_TIMEOUT / 2)) {
+			outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
+			     SMBUS_IO_BASE + SMBHSTSTAT);
 		}
-	} while(--loops);
-	return loops?0:-2;
+	} while (--loops);
+	return loops ? 0 : -2;
 }
 
 static int smbus_wait_until_done(void)
@@ -83,16 +101,16 @@ static int smbus_wait_until_done(void)
 	do {
 		unsigned char val;
 		smbus_delay();
-		
+
 		val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-		if ( (val & 1) == 0) {
+		if ((val & 1) == 0) {
 			break;
 		}
-		if ((val & ~((1<<6)|(1<<0)) ) != 0 ) {
+		if ((val & ~((1 << 6) | (1 << 0))) != 0) {
 			break;
 		}
-	} while(--loops);
-	return loops?0:-3;
+	} while (--loops);
+	return loops ? 0 : -3;
 }
 
 static int smbus_read_byte(unsigned device, unsigned address)
@@ -101,12 +119,12 @@ static int smbus_read_byte(unsigned device, unsigned address)
 	unsigned char global_status_register;
 	unsigned char byte;
 
-	/*print_err("smbus_read_byte\r\n");*/
+	/*print_err("smbus_read_byte\r\n"); */
 	if (smbus_wait_until_ready() < 0) {
 		print_err_hex8(-2);
 		return -2;
 	}
-	
+
 	/* setup transaction */
 	/* disable interrupts */
 	outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL);
@@ -115,16 +133,18 @@ static int smbus_read_byte(unsigned device, unsigned address)
 	/* set the command/address... */
 	outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
 	/* set up for a byte data read */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2<<2), SMBUS_IO_BASE + SMBHSTCTL);
+	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2),
+	     SMBUS_IO_BASE + SMBHSTCTL);
 
 	/* clear any lingering errors, so the transaction will run */
 	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
 
-	/* clear the data byte...*/
+	/* clear the data byte... */
 	outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
 
 	/* start a byte read, with interrupts disabled */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
+	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
+	     SMBUS_IO_BASE + SMBHSTCTL);
 	/* poll for it to start */
 	if (smbus_wait_until_active() < 0) {
 		print_err_hex8(-4);
@@ -137,7 +157,7 @@ static int smbus_read_byte(unsigned device, unsigned address)
 		return -3;
 	}
 
-	global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~(1<<6); /* Ignore the In Use Status... */
+	global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~(1 << 6);	/* Ignore the In Use Status... */
 
 	/* read results of transaction */
 	byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
@@ -153,15 +173,17 @@ static int smbus_read_byte(unsigned device, unsigned address)
  */
 	return byte;
 }
+
 #if 0
-static void smbus_write_byte(unsigned device, unsigned address, unsigned char val)
+static void smbus_write_byte(unsigned device, unsigned address,
+			     unsigned char val)
 {
 	if (smbus_wait_until_ready() < 0) {
 		return;
 	}
 
 	/* by LYH */
-	outb(0x37,SMBUS_IO_BASE + SMBHSTSTAT);
+	outb(0x37, SMBUS_IO_BASE + SMBHSTSTAT);
 	/* set the device I'm talking too */
 	outw(((device & 0x7f) << 1) | 0, SMBUS_IO_BASE + SMBHSTADDR);
 
diff --git a/src/southbridge/intel/i82801dx/i82801dx_ide.c b/src/southbridge/intel/i82801dx/i82801dx_ide.c
index bb3510783d..bf879a9c3c 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_ide.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_ide.c
@@ -1,3 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -5,49 +25,58 @@
 #include <device/pci_ops.h>
 #include "i82801dx.h"
 
+typedef struct southbridge_intel_i82801dx_config config_t;
 
 static void ide_init(struct device *dev)
 {
-#if ICH5_SATA_ADDRESS_MAP<=1
-	/* Enable ide devices so the linux ide driver will work */
-	uint16_t word;
-	uint8_t byte;
-	int enable_a=1, enable_b=1;
-
-
-	word = pci_read_config16(dev, 0x40);
-	word &= ~((1 << 15));
-	if (enable_a) {
-		/* Enable first ide interface */
-		word |= (1<<15);
-		printk_debug("IDE0 ");
+	/* Get the chip configuration */
+	config_t *config = dev->chip_info;
+
+	/* Enable IDE devices so the Linux IDE driver will work. */
+	uint16_t ideTimingConfig;
+
+	ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
+	ideTimingConfig &= ~IDE_DECODE_ENABLE;
+	if (!config || config->ide0_enable) {
+		/* Enable primary IDE interface. */
+		ideTimingConfig |= IDE_DECODE_ENABLE;
+		printk_debug("IDE0: Primary IDE interface is enabled\n");
+	} else {
+		printk_info("IDE0: Primary IDE interface is disabled\n");
 	}
-	pci_write_config16(dev, 0x40, word);
-
-        word = pci_read_config16(dev, 0x42);
-        word &= ~((1 << 15));
-        if (enable_b) {
-                /* Enable secondary ide interface */
-                word |= (1<<15);
-                printk_debug("IDE1 ");
-        }
-        pci_write_config16(dev, 0x42, word);
-#endif
+	pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
 
+	ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC);
+	ideTimingConfig &= ~IDE_DECODE_ENABLE;
+	if (!config || config->ide1_enable) {
+		/* Enable secondary IDE interface. */
+		ideTimingConfig |= IDE_DECODE_ENABLE;
+		printk_debug("IDE1: Secondary IDE interface is enabled\n");
+	} else {
+		printk_info("IDE1: Secondary IDE interface is disabled\n");
+	}
+	pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
 }
 
-static struct device_operations ide_ops  = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
+static struct device_operations ide_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
-	.init             = ide_init,
-	.scan_bus         = 0,
-	.enable           = i82801dx_enable,
+	.init = ide_init,
+	.scan_bus = 0,
+	.enable = i82801dx_enable,
 };
 
-static const struct pci_driver ide_driver __pci_driver = {
-	.ops    = &ide_ops,
+/* 82801DB */
+static const struct pci_driver i82801db_ide __pci_driver = {
+	.ops = &ide_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801DBM_IDE,
+	.device = 0x24cb,
 };
 
+/* 82801DBM */
+static const struct pci_driver i82801dbm_ide __pci_driver = {
+	.ops = &ide_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = 0x24ca,
+};
diff --git a/src/southbridge/intel/i82801dx/i82801dx_lpc.c b/src/southbridge/intel/i82801dx/i82801dx_lpc.c
index 59225d2c9a..dc314fbcfb 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_lpc.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_lpc.c
@@ -1,7 +1,25 @@
 /*
- * (C) 2003 Linux Networx, SuSE Linux AG
- * (C) 2004 Tyan Computer
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Linux Networx
+ * Copyright (C) 2004 SuSE Linux AG
+ * Copyright (C) 2004 Tyan Computer
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -12,113 +30,113 @@
 #include <arch/io.h>
 #include "i82801dx.h"
 
-
-
 #define NMI_OFF 0
 
-void i82801dx_enable_ioapic( struct device *dev) 
+void i82801dx_enable_ioapic(struct device *dev)
 {
-        uint32_t dword;
-        volatile uint32_t *ioapic_sba = (volatile uint32_t *)0xfec00000;
-        volatile uint32_t *ioapic_sbd = (volatile uint32_t *)0xfec00010;
-
-        dword = pci_read_config32(dev, GEN_CNTL);
-        dword |= (3 << 7); /* enable ioapic */
-        dword |= (1 <<13); /* coprocessor error enable */
-        dword |= (1 << 1); /* delay transaction enable */
-        dword |= (1 << 2); /* DMA collection buf enable */
-        pci_write_config32(dev, GEN_CNTL, dword);
-        printk_debug("ioapic southbridge enabled %x\n",dword);
-        *ioapic_sba=0;
-        *ioapic_sbd=(2<<24);
-        //lyh *ioapic_sba=3;
-        //lyh *ioapic_sbd=1;    
-        *ioapic_sba=0;
-        dword=*ioapic_sbd;
-        printk_debug("Southbridge apic id = %x\n",dword);
-        if(dword!=(2<<24))
-                die("");
-        //lyh *ioapic_sba=3;
-        //lyh dword=*ioapic_sbd;
-        //lyh printk_debug("Southbridge apic DT = %x\n",dword);
-        //lyh if(dword!=1)
-        //lyh   die("");
-
+	u32 dword;
+	volatile u32 *ioapic_sba = (volatile u32 *)0xfec00000;
+	volatile u32 *ioapic_sbd = (volatile u32 *)0xfec00010;
+
+	dword = pci_read_config32(dev, GEN_CNTL);
+	dword |= (3 << 7);	/* enable ioapic */
+	dword |= (1 << 13);	/* coprocessor error enable */
+	dword |= (1 << 1);	/* delay transaction enable */
+	dword |= (1 << 2);	/* DMA collection buf enable */
+	pci_write_config32(dev, GEN_CNTL, dword);
+	printk_debug("ioapic southbridge enabled %x\n", dword);
+	*ioapic_sba = 0;
+	*ioapic_sbd = (2 << 24);
+	//lyh *ioapic_sba=3;
+	//lyh *ioapic_sbd=1;    
+	*ioapic_sba = 0;
+	dword = *ioapic_sbd;
+	printk_debug("Southbridge apic id = %x\n", dword);
+	if (dword != (2 << 24))
+		die("");
+	//lyh *ioapic_sba=3;
+	//lyh dword=*ioapic_sbd;
+	//lyh printk_debug("Southbridge apic DT = %x\n",dword);
+	//lyh if(dword!=1)
+	//lyh   die("");
 
 }
-void i82801dx_enable_serial_irqs( struct device *dev)
+
+void i82801dx_enable_serial_irqs(struct device *dev)
 {
-        pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0));
+	pci_write_config8(dev, SERIRQ_CNTL,
+			  (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
 }
-void i82801dx_lpc_route_dma( struct device *dev, uint8_t mask) 
+
+void i82801dx_lpc_route_dma(struct device *dev, u8 mask)
 {
-        uint16_t word;
-        int i;
-        word = pci_read_config16(dev, PCI_DMA_CFG);
-        word &= ((1 << 10) - (1 << 8));
-        for(i = 0; i < 8; i++) {
-                if (i == 4)
-                        continue;
-                word |= ((mask & (1 << i))? 3:1) << (i*2);
-        }
-        pci_write_config16(dev, PCI_DMA_CFG, word);
+	u16 word;
+	int i;
+	word = pci_read_config16(dev, PCI_DMA_CFG);
+	word &= ((1 << 10) - (1 << 8));
+	for (i = 0; i < 8; i++) {
+		if (i == 4)
+			continue;
+		word |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
+	}
+	pci_write_config16(dev, PCI_DMA_CFG, word);
 }
+
 void i82801dx_rtc_init(struct device *dev)
 {
-        uint8_t byte;
-        uint32_t dword;
-        int rtc_failed;
-        byte = pci_read_config8(dev, GEN_PMCON_3);
-        rtc_failed = byte & RTC_FAILED;
-        if (rtc_failed) {
-                byte &= ~(1 << 1); /* preserve the power fail state */
-                pci_write_config8(dev, GEN_PMCON_3, byte);
-        }
-        dword = pci_read_config32(dev, GEN_STS);
-        rtc_failed |= dword & (1 << 2);
-        rtc_init(rtc_failed);
+	u8 byte;
+	u32 dword;
+	int rtc_failed;
+	byte = pci_read_config8(dev, GEN_PMCON_3);
+	rtc_failed = byte & RTC_FAILED;
+	if (rtc_failed) {
+		byte &= ~(1 << 1);	/* preserve the power fail state */
+		pci_write_config8(dev, GEN_PMCON_3, byte);
+	}
+	dword = pci_read_config32(dev, GEN_STS);
+	rtc_failed |= dword & (1 << 2);
+	rtc_init(rtc_failed);
 }
 
-
 void i82801dx_1f0_misc(struct device *dev)
 {
-        pci_write_config16(dev, PCICMD, 0x014f);
-        pci_write_config32(dev, PMBASE, 0x00001001);
-        pci_write_config8(dev, ACPI_CNTL, 0x10);
-        pci_write_config32(dev, GPIO_BASE, 0x00001181);
-        pci_write_config8(dev, GPIO_CNTL, 0x10);
-        pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B);
-        pci_write_config8(dev, PIRQE_ROUT, 0x07);
-        pci_write_config8(dev, RTC_CONF, 0x04);
-        pci_write_config8(dev, COM_DEC, 0x10);  //lyh E0->
-        pci_write_config16(dev, LPC_EN, 0x000F);  //LYH 000D->
+	pci_write_config16(dev, PCICMD, 0x014f);
+	pci_write_config32(dev, PMBASE, 0x00001001);
+	pci_write_config8(dev, ACPI_CNTL, 0x10);
+	pci_write_config32(dev, GPIO_BASE, 0x00001181);
+	pci_write_config8(dev, GPIO_CNTL, 0x10);
+	pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B);
+	pci_write_config8(dev, PIRQE_ROUT, 0x07);
+	pci_write_config8(dev, RTC_CONF, 0x04);
+	pci_write_config8(dev, COM_DEC, 0x10);	//lyh E0->
+	pci_write_config16(dev, LPC_EN, 0x000F);	//LYH 000D->
 }
 
 static void enable_hpet(struct device *dev)
 {
 	const unsigned long hpet_address = 0xfed0000;
 
-        uint32_t dword;
-	uint32_t code = (0 & 0x3);
-        
-        dword = pci_read_config32(dev, GEN_CNTL);
-        dword |= (1 << 17); /* enable hpet */
+	u32 dword;
+	u32 code = (0 & 0x3);
+
+	dword = pci_read_config32(dev, GEN_CNTL);
+	dword |= (1 << 17);	/* enable hpet */
 	/*Bits [16:15]Memory Address Range
-	00 FED0_0000h - FED0_03FFh
-	01 FED0_1000h - FED0_13FFh
-	10 FED0_2000h - FED0_23FFh
-	11 FED0_3000h - FED0_33FFh*/
+	   00 FED0_0000h - FED0_03FFh
+	   01 FED0_1000h - FED0_13FFh
+	   10 FED0_2000h - FED0_23FFh
+	   11 FED0_3000h - FED0_33FFh */
 
-        dword &= ~(3 << 15); /* clear it */
-	dword |= (code<<15);
+	dword &= ~(3 << 15);	/* clear it */
+	dword |= (code << 15);
 
-	printk_debug("enabling HPET @0x%x\n", hpet_address | (code <<12) );
+	printk_debug("enabling HPET @0x%x\n", hpet_address | (code << 12));
 }
 
 static void lpc_init(struct device *dev)
 {
-	uint8_t byte;
-	int pwr_on=-1;
+	u8 byte;
+	int pwr_on = -1;
 	int nmi_option;
 
 	/* IO APIC initialization */
@@ -126,24 +144,24 @@ static void lpc_init(struct device *dev)
 
 	i82801dx_enable_serial_irqs(dev);
 
-#ifdef SUSPICIOUS_LOOKING_CODE	
+#ifdef SUSPICIOUS_LOOKING_CODE
 	// The ICH-4 datasheet does not mention this configuration register. 
 	// This code may have been inherited (incorrectly) from code for the AMD 766 southbridge,
 	// which *does* support this functionality.
 
 	/* posted memory write enable */
 	byte = pci_read_config8(dev, 0x46);
-	pci_write_config8(dev, 0x46, byte | (1<<0)); 
+	pci_write_config8(dev, 0x46, byte | (1 << 0));
 #endif
 
 	/* power after power fail */
-	        /* FIXME this doesn't work! */
-        /* Which state do we want to goto after g3 (power restored)?
-         * 0 == S0 Full On
-         * 1 == S5 Soft Off
-         */
-        pci_write_config8(dev, GEN_PMCON_3, pwr_on?0:1);
-        printk_info("set power %s after power fail\n", pwr_on?"on":"off");
+	/* FIXME this doesn't work! */
+	/* Which state do we want to goto after g3 (power restored)?
+	 * 0 == S0 Full On
+	 * 1 == S5 Soft Off
+	 */
+	pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
+	printk_info("set power %s after power fail\n", pwr_on ? "on" : "off");
 #if 0
 	/* Enable Error reporting */
 	/* Set up sync flood detected */
@@ -153,18 +171,18 @@ static void lpc_init(struct device *dev)
 #endif
 
 	/* Set up NMI on errors */
-    byte = inb(0x61);
-    byte &= ~(1 << 3); /* IOCHK# NMI Enable */
-    byte &= ~(1 << 2); /* PCI SERR# Enable */
-    outb(byte, 0x61);
-    byte = inb(0x70);
+	byte = inb(0x61);
+	byte &= ~(1 << 3);	/* IOCHK# NMI Enable */
+	byte &= ~(1 << 2);	/* PCI SERR# Enable */
+	outb(byte, 0x61);
+	byte = inb(0x70);
 	nmi_option = NMI_OFF;
 	get_option(&nmi_option, "nmi");
-	if (nmi_option) {			
-        byte &= ~(1 << 7); /* set NMI */
-        outb(byte, 0x70);
+	if (nmi_option) {
+		byte &= ~(1 << 7);	/* set NMI */
+		outb(byte, 0x70);
 	}
-	
+
 	/* Initialize the real time clock */
 	i82801dx_rtc_init(dev);
 
@@ -190,15 +208,15 @@ static void i82801dx_lpc_read_resources(device_t dev)
 	res->base = 0;
 	res->size = 0x1000;
 	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
-		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+	    IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 	res->base = 0xff800000;
-	res->size = 0x00800000; /* 8 MB for flash */
+	res->size = 0x00800000;	/* 8 MB for flash */
 	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
-		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+	    IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
-	res = new_resource(dev, 3); /* IOAPIC */
+	res = new_resource(dev, 3);	/* IOAPIC */
 	res->base = 0xfec00000;
 	res->size = 0x00001000;
 	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
@@ -210,17 +228,25 @@ static void i82801dx_lpc_enable_resources(device_t dev)
 	enable_childrens_resources(dev);
 }
 
-static struct device_operations lpc_ops  = {
-	.read_resources   = i82801dx_lpc_read_resources,
-	.set_resources    = pci_dev_set_resources,
+static struct device_operations lpc_ops = {
+	.read_resources = i82801dx_lpc_read_resources,
+	.set_resources = pci_dev_set_resources,
 	.enable_resources = i82801dx_lpc_enable_resources,
-	.init             = lpc_init,
-	.scan_bus         = scan_static_bus,
-	.enable           = i82801dx_enable,
+	.init = lpc_init,
+	.scan_bus = scan_static_bus,
+	.enable = i82801dx_enable,
+};
+
+/* 82801DB/DBL */
+static const struct pci_driver lpc_driver_db __pci_driver = {
+	.ops = &lpc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801DB_LPC,
 };
 
-static const struct pci_driver lpc_driver __pci_driver = {
-	.ops    = &lpc_ops,
+/* 82801DBM */
+static const struct pci_driver lpc_driver_dbm __pci_driver = {
+	.ops = &lpc_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
 	.device = PCI_DEVICE_ID_INTEL_82801DBM_LPC,
 };
diff --git a/src/southbridge/intel/i82801dx/i82801dx_nic.c b/src/southbridge/intel/i82801dx/i82801dx_nic.c
deleted file mode 100644
index 6221ba4889..0000000000
--- a/src/southbridge/intel/i82801dx/i82801dx_nic.c
+++ /dev/null
@@ -1,21 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "i82801dx.h"
-
-
-static struct device_operations nic_ops  = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = 0,
-	.scan_bus         = 0,
-};
-
-static const struct pci_driver nic_driver __pci_driver = {
-	.ops    = &nic_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x103a,
-};
diff --git a/src/southbridge/intel/i82801dx/i82801dx_pci.c b/src/southbridge/intel/i82801dx/i82801dx_pci.c
index 0c88bf2827..610ec1e5df 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_pci.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_pci.c
@@ -1,3 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -11,23 +30,29 @@ static void pci_init(struct device *dev)
 	uint32_t dword;
 	/* System error enable */
 	dword = pci_read_config32(dev, 0x04);
-	dword |= (1<<8); /* SERR# Enable */
-	dword |= (1<<6); /* Parity Error Response */
+	dword |= (1 << 8);	/* SERR# Enable */
+	dword |= (1 << 6);	/* Parity Error Response */
 	pci_write_config32(dev, 0x04, dword);
-
 }
 
-static struct device_operations pci_ops  = {
-	.read_resources   = pci_bus_read_resources,
-	.set_resources    = pci_dev_set_resources,
+static struct device_operations pci_ops = {
+	.read_resources = pci_bus_read_resources,
+	.set_resources = pci_dev_set_resources,
 	.enable_resources = pci_bus_enable_resources,
-	.init             = pci_init,
-	.scan_bus         = pci_scan_bridge,
+	.init = pci_init,
+	.scan_bus = pci_scan_bridge,
 };
 
-static const struct pci_driver pci_driver __pci_driver = {
-	.ops    = &pci_ops,
+/* 82801DB */
+static const struct pci_driver pci_driver_db __pci_driver = {
+	.ops = &pci_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801DBM_PCI,
+	.device = PCI_DEVICE_ID_INTEL_82801DB_PCI,
 };
 
+/* 82801DBM/DBL */
+static const struct pci_driver pci_driver_dbm __pci_driver = {
+	.ops = &pci_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801DBM_PCI,
+};
diff --git a/src/southbridge/intel/i82801dx/i82801dx_reset.c b/src/southbridge/intel/i82801dx/i82801dx_reset.c
index 3d7a4b79b6..3d5c600289 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_reset.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_reset.c
@@ -1,7 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
 #include <arch/io.h>
 
 void hard_reset(void)
 {
-        /* Try rebooting through port 0xcf9 */
-        outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
+	/* Try rebooting through port 0xcf9 */
+	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
 }
diff --git a/src/southbridge/intel/i82801dx/i82801dx_sata.c b/src/southbridge/intel/i82801dx/i82801dx_sata.c
deleted file mode 100644
index 22c6cd77fd..0000000000
--- a/src/southbridge/intel/i82801dx/i82801dx_sata.c
+++ /dev/null
@@ -1,75 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "i82801dx.h"
-
-static void sata_init(struct device *dev)
-{
-
-        uint16_t word;
-        uint8_t byte;
-	int enable_c=1, enable_d=1;
-	//	int i;
-                
-        //Enable Serial ATA port
-        byte = pci_read_config8(dev,0x90);
-        byte &= 0xf8;
-        byte |= ICH5_SATA_ADDRESS_MAP & 7;
-        pci_write_config8(dev,0x90,byte);
-
-//        for(i=0;i<10;i++) {
-		word = pci_read_config16(dev,0x92);
-                word &= 0xfffc;
-//                if( (word & 0x0003) == 0x0003) break;
-                word |= 0x0003; // enable P0/P1 
-                pci_write_config16(dev,0x92,word);
-//        }
-
-//        for(i=0;i<10;i++) {
-              /* enable ide0 */
-		word = pci_read_config16(dev, 0x40);
-        	word &= ~(1 << 15);
-                if(enable_c==0) {
-//                     	if( (word & 0x8000) == 0x0000) break;
-                       	word |= 0x0000;
-                }
-                else {
-//                       	if( (word & 0x8000) == 0x8000) break;
-                       	word |= 0x8000;
-                }
-                pci_write_config16(dev, 0x40, word);
-//	}
-                /* enable ide1 */
-//        for(i=0;i<10;i++) {
-              	word = pci_read_config16(dev, 0x42);
-                word &= ~(1 << 15);
-                if(enable_d==0) {
-//                       	if( (word & 0x8000) == 0x0000) break;
-                       	word |= 0x0000;
-                }
-                else {
-//                       	if( (word & 0x8000) == 0x8000) break;
-                       	word |= 0x8000;
-                }
-                pci_write_config16(dev, 0x42, word);
-//        }
-
-}
-
-static struct device_operations sata_ops  = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = sata_init,
-	.scan_bus         = 0,
-	.enable           = i82801dx_enable,
-};
-
-static const struct pci_driver stat_driver __pci_driver = {
-	.ops    = &sata_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801DBM_SATA,
-};
-
diff --git a/src/southbridge/intel/i82801dx/i82801dx_smbus.c b/src/southbridge/intel/i82801dx/i82801dx_smbus.c
index e56a67c1e0..1f7e47be95 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_smbus.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_smbus.c
@@ -1,3 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
 #include "i82801dx.h"
 #include <smbus.h>
 #include <pci.h>
@@ -6,29 +25,18 @@
 #define PM_BUS 0
 #define PM_DEVFN PCI_DEVFN(0x1f,3)
 
-#if 0
-#define SMBUS_IO_BASE 0x1000
-#define SMBHSTSTAT 0
-#define SMBHSTCTL  2
-#define SMBHSTCMD  3
-#define SMBHSTADD  4
-#define SMBHSTDAT0 5
-#define SMBHSTDAT1 6
-#define SMBBLKDAT  7
-#endif
-
 void smbus_enable(void)
 {
 	unsigned char byte;
 	/* iobase addr */
 	pcibios_write_config_dword(PM_BUS, PM_DEVFN, 0x20, SMBUS_IO_BASE | 1);
 	/* smbus enable */
-	pcibios_write_config_byte(PM_BUS, PM_DEVFN, 0x40,  1);
+	pcibios_write_config_byte(PM_BUS, PM_DEVFN, 0x40, 1);
 	/* iospace enable */
 	pcibios_write_config_word(PM_BUS, PM_DEVFN, 0x4, 1);
 
-        /* Disable interrupt generation */
-        outb(0, SMBUS_IO_BASE + SMBHSTCTL);
+	/* Disable interrupt generation */
+	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
 
 }
 
@@ -39,7 +47,7 @@ void smbus_setup(void)
 
 static void smbus_wait_until_ready(void)
 {
-	while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) {
+	while ((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) {
 		/* nop */
 	}
 }
@@ -50,8 +58,8 @@ static void smbus_wait_until_done(void)
 	do {
 		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
 	}
-	while((byte &1) == 1);
-	while( (byte & ~1) == 0) {
+	while ((byte & 1) == 1);
+	while ((byte & ~1) == 0) {
 		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
 	}
 }
@@ -71,16 +79,18 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
 	/* set the command/address... */
 	outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
 	/* set up for a byte data read */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL);
+	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2),
+	     SMBUS_IO_BASE + SMBHSTCTL);
 
 	/* clear any lingering errors, so the transaction will run */
 	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
 
-	/* clear the data byte...*/
+	/* clear the data byte... */
 	outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
 
 	/* start the command */
-	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
+	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
+	     SMBUS_IO_BASE + SMBHSTCTL);
 
 	/* poll for transaction completion */
 	smbus_wait_until_done();
diff --git a/src/southbridge/intel/i82801dx/i82801dx_tco_timer.c b/src/southbridge/intel/i82801dx/i82801dx_tco_timer.c
index ea5485f799..1d4d7640a1 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_tco_timer.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_tco_timer.c
@@ -3,9 +3,10 @@
  *
  * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -14,8 +15,8 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- *
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
  */
 
 static void i82801dx_halt_tco_timer(void)
@@ -33,5 +34,6 @@ static void i82801dx_halt_tco_timer(void)
 	pci_write_config8(dev, ACPI_CNTL, 0x10);
 
 	/* Halt the TCO timer, preventing SMI and automatic reboot */
-	outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11), PMBASE_ADDR + TCOBASE + TCO1_CNT);
+	outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11),
+	     PMBASE_ADDR + TCOBASE + TCO1_CNT);
 }
diff --git a/src/southbridge/intel/i82801dx/i82801dx_usb.c b/src/southbridge/intel/i82801dx/i82801dx_usb.c
index 2e60193855..48b990d1ac 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_usb.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_usb.c
@@ -1,3 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -7,43 +28,41 @@
 
 static void usb_init(struct device *dev)
 {
-
-
-#if 0
-	uint32_t cmd;
+	u32 cmd;
 	printk_debug("USB: Setting up controller.. ");
 	cmd = pci_read_config32(dev, PCI_COMMAND);
-	pci_write_config32(dev, PCI_COMMAND, 
-		cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 
-		PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
-
-
+	pci_write_config32(dev, PCI_COMMAND,
+			   cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+			   PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
 	printk_debug("done.\n");
-#endif
-
 }
 
-static struct device_operations usb_ops  = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
+static struct device_operations usb_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
-	.init             = usb_init,
-	.scan_bus         = 0,
-	.enable           = i82801dx_enable,
+	.init = usb_init,
+	.scan_bus = 0,
+	.enable = i82801dx_enable,
 };
 
+/* 82801DB/DBL/DBM USB1 */
 static const struct pci_driver usb_driver_1 __pci_driver = {
-	.ops    = &usb_ops,
+	.ops = &usb_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801DBM_USB1,
+	.device = PCI_DEVICE_ID_INTEL_82801DB_USB1,
 };
+
+/* 82801DB/DBL/DBM USB2 */
 static const struct pci_driver usb_driver_2 __pci_driver = {
-        .ops    = &usb_ops,
-        .vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801DBM_USB2,
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801DB_USB2,
 };
+
+/* 82801DB/DBL/DBM USB3 */
 static const struct pci_driver usb_driver_3 __pci_driver = {
-        .ops    = &usb_ops,
-        .vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801DBM_USB3,
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82801DB_USB3,
 };
diff --git a/src/southbridge/intel/i82801dx/i82801dx_usb2.c b/src/southbridge/intel/i82801dx/i82801dx_usb2.c
index ca13e92995..96bbd7748d 100644
--- a/src/southbridge/intel/i82801dx/i82801dx_usb2.c
+++ b/src/southbridge/intel/i82801dx/i82801dx_usb2.c
@@ -1,4 +1,23 @@
-//2003 Copywright Tyan
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Tyan
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
 
 #include <console/console.h>
 #include <device/device.h>
@@ -9,32 +28,27 @@
 
 static void usb2_init(struct device *dev)
 {
-
-
-#if 0  
-  uint32_t cmd;
+	u32 cmd;
 	printk_debug("USB: Setting up controller.. ");
 	cmd = pci_read_config32(dev, PCI_COMMAND);
-	pci_write_config32(dev, PCI_COMMAND, 
-		cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 
-		PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
-
-
+	pci_write_config32(dev, PCI_COMMAND,
+			   cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+			   PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
 	printk_debug("done.\n");
-#endif
 }
 
-static struct device_operations usb2_ops  = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
+static struct device_operations usb2_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
-	.init             = usb2_init,
-	.scan_bus         = 0,
-	.enable           = i82801dx_enable,
+	.init = usb2_init,
+	.scan_bus = 0,
+	.enable = i82801dx_enable,
 };
 
+/* 82801DB/DBM USB 2.0 */
 static const struct pci_driver usb2_driver __pci_driver = {
-	.ops    = &usb2_ops,
+	.ops = &usb2_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_82801DBM_EHCI,
+	.device = PCI_DEVICE_ID_INTEL_82801DB_EHCI,
 };