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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-23 07:23:40 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-06 09:24:11 +0000 |
commit | c328a680def0f589536c24ff547465bd7eb3546d (patch) | |
tree | fa81f3b8f83b9fd408435d2b085b40d8655d68a0 /src/southbridge/intel | |
parent | 2e270ae2974463c86711b400a7abcb36d1b2e67d (diff) | |
download | coreboot-c328a680def0f589536c24ff547465bd7eb3546d.tar.xz |
soc,southbridge/intel: Control SMI related FADT entries
When no SMI is installed, FADT should not advertise a trigger
mechanism that does not respond.
Change-Id: Ifb4f99c11a72e75ec20b9faaf62aed5546de91fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41909
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r-- | src/southbridge/intel/bd82x6x/lpc.c | 12 | ||||
-rw-r--r-- | src/southbridge/intel/i82371eb/fadt.c | 11 | ||||
-rw-r--r-- | src/southbridge/intel/i82801gx/lpc.c | 14 | ||||
-rw-r--r-- | src/southbridge/intel/i82801jx/lpc.c | 14 | ||||
-rw-r--r-- | src/southbridge/intel/ibexpeak/lpc.c | 12 | ||||
-rw-r--r-- | src/southbridge/intel/lynxpoint/lpc.c | 12 |
6 files changed, 39 insertions, 36 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 55e2573eff..45215f1c94 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -697,11 +697,12 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->reserved = 0; fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + } fadt->pm1a_evt_blk = pmbase; fadt->pm1b_evt_blk = 0x0; @@ -719,7 +720,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->gpe0_blk_len = 16; fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; c2_latency = chip->c2_latency; if (!c2_latency) { c2_latency = 101; /* c2 unsupported */ diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 921edf3c5a..09e027f407 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -35,11 +35,11 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->dsdt = (uintptr_t)dsdt; fadt->preferred_pm_profile = 0; /* unspecified */ fadt->sci_int = 9; - fadt->smi_cmd = 0; /* smi command port */ - fadt->acpi_enable = 0; /* acpi enable smi command */ - fadt->acpi_disable = 0; /* acpi disable smi command */ - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0x0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + /* TODO: SMI handler is not implemented. */ + fadt->smi_cmd = 0x00; + } fadt->pm1a_evt_blk = DEFAULT_PMBASE; fadt->pm1b_evt_blk = 0x0; @@ -60,7 +60,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 4; - fadt->cst_cnt = 0; /* smi command to indicate c state changed notification */ fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */ fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */ fadt->flush_size = 0; /* only needed if CPU wbinvd is broken */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 7e2b5a7ca6..86c3e58750 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -521,13 +521,15 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->reserved = 0; fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = APM_CNT_PST_CONTROL; - fadt->cst_cnt = APM_CNT_CST_CONTROL; + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->pstate_cnt = APM_CNT_PST_CONTROL; + fadt->cst_cnt = APM_CNT_CST_CONTROL; + } + fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = chip->c3_latency; fadt->flush_size = 0; diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index ae98fddc2a..b3aeda22f7 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -532,13 +532,15 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->reserved = 0; fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = APM_CNT_PST_CONTROL; - fadt->cst_cnt = APM_CNT_CST_CONTROL; + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->cst_cnt = APM_CNT_CST_CONTROL; + fadt->pstate_cnt = APM_CNT_PST_CONTROL; + } + fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = chip->c3_latency; fadt->flush_size = 0; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 54b2621bca..1209f9b685 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -591,11 +591,12 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->reserved = 0; fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + } fadt->pm1a_evt_blk = pmbase; fadt->pm1b_evt_blk = 0x0; @@ -613,7 +614,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->gpe0_blk_len = 16; fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; c2_latency = chip->c2_latency; if (!c2_latency) { c2_latency = 101; /* c2 unsupported */ diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 7e1355a7d5..da744bfa64 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -740,11 +740,12 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) u16 pmbase = get_pmbase(); fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; + + if (CONFIG(HAVE_SMI_HANDLER)) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + } fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1b_evt_blk = 0x0; @@ -775,7 +776,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0; fadt->p_lvl2_lat = 1; fadt->p_lvl3_lat = 87; fadt->flush_size = 0; |