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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-02-07 17:38:45 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-02-14 22:37:59 +0100 |
| commit | 24501cae529a51ab9304721be0ec60384ab81ee0 (patch) | |
| tree | 0317f32ac6174b914b0e4400e63fd64f392059ee /src/southbridge/intel | |
| parent | 41cd047cd25b5fbb02da3e37b9dc2ca6ca90e34e (diff) | |
| download | coreboot-24501cae529a51ab9304721be0ec60384ab81ee0.tar.xz | |
AMD cimx/sb800: Initially enable all GPP ports
PCIe root ports on devices 0:15.0 to 0:15.3 should at first all
appear visible in hardware. The real configuration will be done by
vendorcode once we call sb_Before_Pci_Init().
Change-Id: I01a46c630aa6d55a94af45da6b78c97df7553e4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8387
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/southbridge/intel')
0 files changed, 0 insertions, 0 deletions