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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-07-14 17:43:52 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2019-07-26 21:16:13 +0000 |
| commit | 403f4332382f36f3b63e9ed8715b4f5604627c97 (patch) | |
| tree | 827c7e1bea7168687630a188d29ec8e5057b79c7 /src/southbridge/intel | |
| parent | ae5b3671b39f26b79685496d79845f9a4f3975db (diff) | |
| download | coreboot-403f4332382f36f3b63e9ed8715b4f5604627c97.tar.xz | |
sb/intel/bd82x6x: Add support to disable xHCI
Set FD bit if xHCI is disabled in devicetree.
Change-Id: I3d08ded10daea6d86857ebbbf3f8dcc85ebe9df4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index f8540af451..e4eccd766d 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -148,6 +148,12 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) static void pch_hide_devfn(unsigned devfn) { switch (devfn) { + case PCI_DEVFN(20, 0): /* xHCI */ + if (pch_silicon_type() == PCH_TYPE_PPT) { + /* on CPT this bit is reserved */ + RCBA32_OR(FD, PCH_DISABLE_XHCI); + } + break; case PCI_DEVFN(22, 0): /* MEI #1 */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); break; |