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| author | Matt DeVillier <matt.devillier@gmail.com> | 2017-04-17 18:25:09 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-05-31 19:09:50 +0200 |
| commit | 8b96fd2e5affcf4420268d53fa58826685ccbeed (patch) | |
| tree | ca67b34592d823f59a2229a37d030513c57adaf0 /src/southbridge/intel | |
| parent | c5bd8b359b85177c965c1c0dfaeddca902b3b38c (diff) | |
| download | coreboot-8b96fd2e5affcf4420268d53fa58826685ccbeed.tar.xz | |
sb/lynxpoint: add ACPI method to generate USB port info
Add ACPI method GPLD to generate port location data when
passed visiblity info. Will be used by _PLD method in
board-specific USB .asl files.
Change-Id: If63d5637a0469eeace0d935cca961e8d04fdfb1a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/acpi/usb.asl | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl index b02cbfea3b..85e439036f 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl @@ -393,6 +393,22 @@ Device (XHCI) { Name (_ADR, 0x00000000) + // GPLD: Generate Port Location Data (PLD) + Method (GPLD, 1, Serialized) { + Name (PCKG, Package (0x01) { + Buffer (0x10) {} + }) + + // REV: Revision 0x02 for ACPI 5.0 + CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) + Store (0x02, REV) + + // VISI: Port visibility to user per port + CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) + Store (Arg0, VISI) + Return (PCKG) + } + // How many are there? Device (PRT1) { Name (_ADR, 1) } // USB Port 0 Device (PRT2) { Name (_ADR, 2) } // USB Port 1 |