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| author | Myles Watson <mylesgw@gmail.com> | 2009-11-06 23:42:26 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2009-11-06 23:42:26 +0000 |
| commit | d27c08c2898d1d74765a7799628d1c18369fd671 (patch) | |
| tree | 7ac357d2b44d833c6efe70d1e691c6611c521e8d /src/southbridge/nvidia/ck804/chip.h | |
| parent | 547d48ab01049a634dccb16d1847524d5ba93e33 (diff) | |
| download | coreboot-d27c08c2898d1d74765a7799628d1c18369fd671.tar.xz | |
Remove drivers/pci/onboard. The only purpose was for option ROMs, which are
now handled more generically using CBFS.
Simplify the option ROM code in device/pci_rom.c, since there are only two ways
to get a ROM address now (CBFS and the device) and add an exception for qemu.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/nvidia/ck804/chip.h')
| -rw-r--r-- | src/southbridge/nvidia/ck804/chip.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/southbridge/nvidia/ck804/chip.h b/src/southbridge/nvidia/ck804/chip.h index ddbe6be981..479f3ebbf4 100644 --- a/src/southbridge/nvidia/ck804/chip.h +++ b/src/southbridge/nvidia/ck804/chip.h @@ -7,8 +7,6 @@ struct southbridge_nvidia_ck804_config { unsigned int ide1_enable : 1; unsigned int sata0_enable : 1; unsigned int sata1_enable : 1; - unsigned long nic_rom_address; - unsigned long raid_rom_address; unsigned int mac_eeprom_smbus; unsigned int mac_eeprom_addr; }; |