diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-01-16 17:53:38 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-01-16 17:53:38 +0000 |
| commit | 9fe4d797a37671a65053add3f7cca27397db0b9b (patch) | |
| tree | 5cabbdc8b6e7eb970891b55d1ea3727a4a71aca2 /src/southbridge/nvidia/ck804 | |
| parent | 984e0f3a0c3a82339ef8afcf7f315f377e0c81fc (diff) | |
| download | coreboot-9fe4d797a37671a65053add3f7cca27397db0b9b.tar.xz | |
coreboot used to have two different "APIs" for memory accesses:
read32(unsigned long addr) vs readl(void *addr)
and
write32(unsigned long addr, uint32_t value) vs writel(uint32_t value, void *addr)
read32 was only available in __PRE_RAM__ stage, while readl was used in stage2.
Some unclean implementations then made readl available to __PRE_RAM__ too which
results in really messy includes and code.
This patch fixes all code to use the read32/write32 variant, so that we can
remove readl/writel in another patch.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/nvidia/ck804')
| -rw-r--r-- | src/southbridge/nvidia/ck804/ck804_nic.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/nvidia/ck804/ck804_nic.c b/src/southbridge/nvidia/ck804/ck804_nic.c index 4ad0d11a62..cb8015c16b 100644 --- a/src/southbridge/nvidia/ck804/ck804_nic.c +++ b/src/southbridge/nvidia/ck804/ck804_nic.c @@ -27,7 +27,7 @@ static void nic_init(struct device *dev) #define NvRegPhyInterface 0xC0 #define PHY_RGMII 0x10000000 - writel(PHY_RGMII, base + NvRegPhyInterface); + write32(base + NvRegPhyInterface, PHY_RGMII); old = dword = pci_read_config32(dev, 0x30); dword &= ~(0xf); @@ -76,15 +76,15 @@ static void nic_init(struct device *dev) if (!eeprom_valid) { unsigned long mac_pos; mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */ - mac_l = readl((uint8_t*)mac_pos) + nic_index; - mac_h = readl((uint8_t*)mac_pos + 4); + mac_l = read32((uint8_t*)mac_pos) + nic_index; + mac_h = read32((uint8_t*)mac_pos + 4); } #if 1 /* Set that into NIC MMIO. */ #define NvRegMacAddrA 0xA8 #define NvRegMacAddrB 0xAC - writel(mac_l, base + NvRegMacAddrA); - writel(mac_h, base + NvRegMacAddrB); + write32(base + NvRegMacAddrA, mac_l); + write32(base + NvRegMacAddrB, mac_h); #else /* Set that into NIC. */ pci_write_config32(dev, 0xa8, mac_l); |