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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-19 17:28:43 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-20 19:06:28 +0000 |
| commit | 1ca978ee6529251ed80b47da679be7adc75fa46a (patch) | |
| tree | 6a74b87cba9ea22d67ecba3c1cb0096c515c3c62 /src/southbridge/nvidia/mcp55/chip.h | |
| parent | 185691eedb37ae26f7829d762cd476395be57f5d (diff) | |
| download | coreboot-1ca978ee6529251ed80b47da679be7adc75fa46a.tar.xz | |
sb/nvidia/mcp55: Drop support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which platforms using this code lack.
Change-Id: I7cd33316140f2cdc83949aa5db7e6f1565982543
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36973
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/nvidia/mcp55/chip.h')
| -rw-r--r-- | src/southbridge/nvidia/mcp55/chip.h | 31 |
1 files changed, 0 insertions, 31 deletions
diff --git a/src/southbridge/nvidia/mcp55/chip.h b/src/southbridge/nvidia/mcp55/chip.h deleted file mode 100644 index 4bc8428a1a..0000000000 --- a/src/southbridge/nvidia/mcp55/chip.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SOUTHBRIDGE_NVIDIA_MCP55_CHIP_H -#define SOUTHBRIDGE_NVIDIA_MCP55_CHIP_H - -struct southbridge_nvidia_mcp55_config -{ - unsigned int ide0_enable : 1; - unsigned int ide1_enable : 1; - unsigned int sata0_enable : 1; - unsigned int sata1_enable : 1; - unsigned int mac_eeprom_smbus; - unsigned int mac_eeprom_addr; -}; - -#endif |