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authorArthur Heymans <arthur@aheymans.xyz>2019-11-19 17:28:43 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-20 19:06:28 +0000
commit1ca978ee6529251ed80b47da679be7adc75fa46a (patch)
tree6a74b87cba9ea22d67ecba3c1cb0096c515c3c62 /src/southbridge/nvidia/mcp55/pcie.c
parent185691eedb37ae26f7829d762cd476395be57f5d (diff)
downloadcoreboot-1ca978ee6529251ed80b47da679be7adc75fa46a.tar.xz
sb/nvidia/mcp55: Drop support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I7cd33316140f2cdc83949aa5db7e6f1565982543 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36973 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/nvidia/mcp55/pcie.c')
-rw-r--r--src/southbridge/nvidia/mcp55/pcie.c61
1 files changed, 0 insertions, 61 deletions
diff --git a/src/southbridge/nvidia/mcp55/pcie.c b/src/southbridge/nvidia/mcp55/pcie.c
deleted file mode 100644
index 0a352443b4..0000000000
--- a/src/southbridge/nvidia/mcp55/pcie.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Tyan Computer
- * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
- * Copyright (C) 2006,2007 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "mcp55.h"
-
-static void pcie_init(struct device *dev)
-{
- /* Enable pci error detecting */
- u32 dword;
-
- /* System error enable */
- dword = pci_read_config32(dev, 0x04);
- dword |= (1<<8); /* System error enable */
- dword |= (1<<30); /* Clear possible errors */
- pci_write_config32(dev, 0x04, dword);
-
-}
-
-static struct device_operations pcie_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = pcie_init,
- .scan_bus = pci_scan_bridge,
-// .enable = mcp55_enable,
-};
-
-static const unsigned short pcie_ids[] = {
- PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C,
- PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E,
- PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A,
- PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F,
- PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D,
- 0
-};
-
-static const struct pci_driver pciebc_driver __pci_driver = {
- .ops = &pcie_ops,
- .vendor = PCI_VENDOR_ID_NVIDIA,
- .devices= pcie_ids,
-};