diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2010-01-16 18:31:34 +0000 |
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committer | Stefan Reinauer <stepan@openbios.org> | 2010-01-16 18:31:34 +0000 |
commit | 0401bd89b6e7105ca597a221fdbe2a8b75c35296 (patch) | |
tree | ec342f9dcaae2619bcb06a57789a07328402ea71 /src/southbridge/nvidia/mcp55 | |
parent | 9fe4d797a37671a65053add3f7cca27397db0b9b (diff) | |
download | coreboot-0401bd89b6e7105ca597a221fdbe2a8b75c35296.tar.xz |
coreboot has 13 instances of IOAPIC setup distributed across a lot
of components. This patch is a rewrite of the generic IOAPIC setup code.
Additionally it drops the other 12 instances of IOAPIC setup code and
makes the components use the generic code.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/nvidia/mcp55')
-rw-r--r-- | src/southbridge/nvidia/mcp55/mcp55_lpc.c | 95 |
1 files changed, 7 insertions, 88 deletions
diff --git a/src/southbridge/nvidia/mcp55/mcp55_lpc.c b/src/southbridge/nvidia/mcp55/mcp55_lpc.c index a9e6c36991..c247d98be1 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_lpc.c +++ b/src/southbridge/nvidia/mcp55/mcp55_lpc.c @@ -33,97 +33,13 @@ #include <pc80/isa-dma.h> #include <bitops.h> #include <arch/io.h> +#include <arch/ioapic.h> #include <cpu/x86/lapic.h> #include <stdlib.h> #include "mcp55.h" #define NMI_OFF 0 -struct ioapicreg { - unsigned int reg; - unsigned int value_low, value_high; -}; - -static struct ioapicreg ioapicregvalues[] = { -#define ALL (0xff << 24) -#define NONE (0) -#define DISABLED (1 << 16) -#define ENABLED (0 << 16) -#define TRIGGER_EDGE (0 << 15) -#define TRIGGER_LEVEL (1 << 15) -#define POLARITY_HIGH (0 << 13) -#define POLARITY_LOW (1 << 13) -#define PHYSICAL_DEST (0 << 11) -#define LOGICAL_DEST (1 << 11) -#define ExtINT (7 << 8) -#define NMI (4 << 8) -#define SMI (2 << 8) -#define INT (1 << 8) - /* IO-APIC virtual wire mode configuration */ - /* mask, trigger, polarity, destination, delivery, vector */ - { 0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE}, - { 1, DISABLED, NONE}, - { 2, DISABLED, NONE}, - { 3, DISABLED, NONE}, - { 4, DISABLED, NONE}, - { 5, DISABLED, NONE}, - { 6, DISABLED, NONE}, - { 7, DISABLED, NONE}, - { 8, DISABLED, NONE}, - { 9, DISABLED, NONE}, - { 10, DISABLED, NONE}, - { 11, DISABLED, NONE}, - { 12, DISABLED, NONE}, - { 13, DISABLED, NONE}, - { 14, DISABLED, NONE}, - { 15, DISABLED, NONE}, - { 16, DISABLED, NONE}, - { 17, DISABLED, NONE}, - { 18, DISABLED, NONE}, - { 19, DISABLED, NONE}, - { 20, DISABLED, NONE}, - { 21, DISABLED, NONE}, - { 22, DISABLED, NONE}, - { 23, DISABLED, NONE}, - /* Be careful and don't write past the end... */ -}; - -static void setup_ioapic(unsigned long ioapic_base, int master) -{ - int i; - unsigned long value_low, value_high; -// unsigned long ioapic_base = 0xfec00000; - volatile unsigned long *l; - struct ioapicreg *a = ioapicregvalues; - - if (master) { - ioapicregvalues[0].value_high = lapicid()<<(56-32); - ioapicregvalues[0].value_low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT; - } - else { - ioapicregvalues[0].value_high = NONE; - ioapicregvalues[0].value_low = DISABLED; - } - - l = (unsigned long *) ioapic_base; - - for (i = 0; i < ARRAY_SIZE(ioapicregvalues); - i++, a++) { - l[0] = (a->reg * 2) + 0x10; - l[4] = a->value_low; - value_low = l[4]; - l[0] = (a->reg *2) + 0x11; - l[4] = a->value_high; - value_high = l[4]; - if ((i==0) && (value_low == 0xffffffff)) { - printk_warning("IO APIC not responding.\n"); - return; - } - printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n", - a->reg, a->value_low, a->value_high); - } -} - // 0x7a or e3 #define PREVIOUS_POWER_STATE 0x7A @@ -139,15 +55,18 @@ static void setup_ioapic(unsigned long ioapic_base, int master) static void lpc_common_init(device_t dev, int master) { uint8_t byte; - uint32_t dword; + uint32_t ioapic_base; /* IO APIC initialization */ byte = pci_read_config8(dev, 0x74); byte |= (1<<0); // enable APIC pci_write_config8(dev, 0x74, byte); - dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14 + ioapic_base = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14 - setup_ioapic(dword, master); + if (master) + setup_ioapic(ioapic_base, 0); + else + clear_ioapic(ioapic_base); } static void lpc_slave_init(device_t dev) |