diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-04-26 22:16:42 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2018-04-29 16:46:38 +0000 |
| commit | 64e091fc8a5f9044995de58a5780342fbeb2acf8 (patch) | |
| tree | 3b82ade92a6cfea6af9f8d98f4c8fa7608c2a42e /src/southbridge/nvidia | |
| parent | 6c4861859761e1110e9651b989a521152394fcf3 (diff) | |
| download | coreboot-64e091fc8a5f9044995de58a5780342fbeb2acf8.tar.xz | |
southbridge/nvidia: Remove spaces before/after parenthesis
Change-Id: I94a87d631c9336b861523592ff217fe823436b36
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge/nvidia')
| -rw-r--r-- | src/southbridge/nvidia/ck804/acpi/ck804.asl | 4 | ||||
| -rw-r--r-- | src/southbridge/nvidia/mcp55/early_setup_car.c | 4 | ||||
| -rw-r--r-- | src/southbridge/nvidia/mcp55/lpc.c | 2 | ||||
| -rw-r--r-- | src/southbridge/nvidia/mcp55/smbus.h | 2 |
4 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/nvidia/ck804/acpi/ck804.asl b/src/southbridge/nvidia/ck804/acpi/ck804.asl index aac7ea8bad..4a83b8481e 100644 --- a/src/southbridge/nvidia/ck804/acpi/ck804.asl +++ b/src/southbridge/nvidia/ck804/acpi/ck804.asl @@ -54,7 +54,7 @@ Method (SRSA, 1, Serialized) { /* set "B", external (PCI) APIC interrupts */ Name (PRSB, ResourceTemplate () { - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) { + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,,) { 16, 17, 18, 19, } }) @@ -93,7 +93,7 @@ Method (SRSB, 1, Serialized) { /* set "C", southbridge APIC interrupts */ Name (PRSC, ResourceTemplate () { - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) { + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,,) { 20, 21, 22, 23, } }) diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 8019a8ef21..6ddd59e850 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -83,7 +83,7 @@ static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, }; int j; - for (j = 0; j < mcp55_num; j++ ) { + for (j = 0; j < mcp55_num; j++) { setup_resource_map_offset(ctrl_devport_conf, ARRAY_SIZE(ctrl_devport_conf), PCI_DEV(busn[j], devn[j], 0) , io_base[j]); @@ -100,7 +100,7 @@ static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn, }; int j; - for (j = 0; j < mcp55_num; j++ ) { + for (j = 0; j < mcp55_num; j++) { setup_resource_map_offset(ctrl_devport_conf_clear, ARRAY_SIZE(ctrl_devport_conf_clear), PCI_DEV(busn[j], devn[j], 0) , io_base[j]); diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index eeb6c1b1d0..180b9a8fd0 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -131,7 +131,7 @@ static void lpc_init(device_t dev) if (nmi_option) byte &= ~(1 << 7); /* Set NMI. */ else - byte |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */ + byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */ if (byte != byte_old) outb(byte, 0x70); diff --git a/src/southbridge/nvidia/mcp55/smbus.h b/src/southbridge/nvidia/mcp55/smbus.h index a588a097f0..274ccfea38 100644 --- a/src/southbridge/nvidia/mcp55/smbus.h +++ b/src/southbridge/nvidia/mcp55/smbus.h @@ -45,7 +45,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base) smbus_delay(); val = inb(smbus_io_base + SMBHSTSTAT); - if ( (val & 0xff) != 0) { + if ((val & 0xff) != 0) { return 0; } } while (--loops); |