summaryrefslogtreecommitdiff
path: root/src/southbridge/nvidia
diff options
context:
space:
mode:
authorUwe Hermann <uwe@hermann-uwe.de>2010-12-09 18:09:14 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-12-09 18:09:14 +0000
commit42b1c43c4dad6a58f444e868b84c6bbd10009681 (patch)
treea1c380d769f64606f7405f3c770ce73770f71c4c /src/southbridge/nvidia
parentd6ecfdbc84298840ded02f5c4d009732786ed847 (diff)
downloadcoreboot-42b1c43c4dad6a58f444e868b84c6bbd10009681.tar.xz
Merge enable_rom.c files into bootblock.c files.
All southbridges using TINY_BOOTBLOCK have a bootblock.c files which simply includes an enable_rom.c files. As discussed on the mailing list, drop the enable_rom.c file by merging it into bootblock.c. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/nvidia')
-rw-r--r--src/southbridge/nvidia/ck804/bootblock.c24
-rw-r--r--src/southbridge/nvidia/ck804/enable_rom.c40
-rw-r--r--src/southbridge/nvidia/mcp55/bootblock.c37
-rw-r--r--src/southbridge/nvidia/mcp55/enable_rom.c54
4 files changed, 57 insertions, 98 deletions
diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c
index 6d4b6a4777..29c10c8d0e 100644
--- a/src/southbridge/nvidia/ck804/bootblock.c
+++ b/src/southbridge/nvidia/ck804/bootblock.c
@@ -1,7 +1,8 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2010 Jonathan Kollasch <jakllsch@kollasch.net>
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -20,7 +21,26 @@
#include <arch/io.h>
#include <arch/romcc_io.h>
-#include "southbridge/nvidia/ck804/enable_rom.c"
+#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
+#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
+#else
+#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
+#endif
+
+static void ck804_enable_rom(void)
+{
+ unsigned char byte;
+ device_t addr;
+
+ /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
+ /* Locate the ck804 LPC. */
+ addr = PCI_DEV(0, (CK804_DEVN_BASE + 1), 0);
+
+ /* Set the 4MB enable bit. */
+ byte = pci_read_config8(addr, 0x88);
+ byte |= 0x80;
+ pci_write_config8(addr, 0x88, byte);
+}
static void bootblock_southbridge_init(void)
{
diff --git a/src/southbridge/nvidia/ck804/enable_rom.c b/src/southbridge/nvidia/ck804/enable_rom.c
deleted file mode 100644
index facf7959eb..0000000000
--- a/src/southbridge/nvidia/ck804/enable_rom.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Tyan Computer
- * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
-#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
-#else
-#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
-#endif
-
-static void ck804_enable_rom(void)
-{
- unsigned char byte;
- device_t addr;
-
- /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
- /* Locate the ck804 LPC. */
- addr = PCI_DEV(0, (CK804_DEVN_BASE + 1), 0);
-
- /* Set the 4MB enable bit. */
- byte = pci_read_config8(addr, 0x88);
- byte |= 0x80;
- pci_write_config8(addr, 0x88, byte);
-}
diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c
index 139f93c99d..b2698496fa 100644
--- a/src/southbridge/nvidia/mcp55/bootblock.c
+++ b/src/southbridge/nvidia/mcp55/bootblock.c
@@ -1,7 +1,10 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2004 Tyan Computer
+ * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
+ * Copyright (C) 2006,2007 AMD
+ * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,7 +21,37 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include "southbridge/nvidia/mcp55/enable_rom.c"
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include "mcp55.h"
+
+static void mcp55_enable_rom(void)
+{
+ uint8_t byte;
+ uint16_t word;
+ device_t addr;
+
+ /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
+#if 0
+ /* default MCP55 LPC single */
+ addr = pci_locate_device(PCI_ID(0x10de, 0x0367), 0);
+#else
+// addr = pci_locate_device(PCI_ID(0x10de, 0x0360), 0);
+ addr = PCI_DEV(0, (MCP55_DEVN_BASE+1), 0);
+#endif
+
+ /* Set the 4MB enable bit bit */
+ byte = pci_read_config8(addr, 0x88);
+ byte |= 0xff; //256K
+ pci_write_config8(addr, 0x88, byte);
+ byte = pci_read_config8(addr, 0x8c);
+ byte |= 0xff; //1M
+ pci_write_config8(addr, 0x8c, byte);
+ word = pci_read_config16(addr, 0x90);
+ word |= 0x7fff; //15M
+ pci_write_config16(addr, 0x90, word);
+}
static void bootblock_southbridge_init(void)
{
diff --git a/src/southbridge/nvidia/mcp55/enable_rom.c b/src/southbridge/nvidia/mcp55/enable_rom.c
deleted file mode 100644
index d08b1d486b..0000000000
--- a/src/southbridge/nvidia/mcp55/enable_rom.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Tyan Computer
- * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
- * Copyright (C) 2006,2007 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include "mcp55.h"
-
-static void mcp55_enable_rom(void)
-{
- uint8_t byte;
- uint16_t word;
- device_t addr;
-
- /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
-#if 0
- /* default MCP55 LPC single */
- addr = pci_locate_device(PCI_ID(0x10de, 0x0367), 0);
-#else
-// addr = pci_locate_device(PCI_ID(0x10de, 0x0360), 0);
- addr = PCI_DEV(0, (MCP55_DEVN_BASE+1), 0);
-#endif
-
- /* Set the 4MB enable bit bit */
- byte = pci_read_config8(addr, 0x88);
- byte |= 0xff; //256K
- pci_write_config8(addr, 0x88, byte);
- byte = pci_read_config8(addr, 0x8c);
- byte |= 0xff; //1M
- pci_write_config8(addr, 0x8c, byte);
- word = pci_read_config16(addr, 0x90);
- word |= 0x7fff; //15M
- pci_write_config16(addr, 0x90, word);
-}