diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-08-21 12:06:54 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-23 15:45:33 +0200 |
| commit | 7f9df96825100059e3ee1bc78f8b7154441b2751 (patch) | |
| tree | 7927ecdbff84593256b829bcbe5d4d191bb687ab /src/southbridge/nvidia | |
| parent | d6e96864c9245b82222dada6fea2b89ccb7fecfd (diff) | |
| download | coreboot-7f9df96825100059e3ee1bc78f8b7154441b2751.tar.xz | |
src/southbridge: Remove unnecessary whitespace before "\n" and "\t"
Change-Id: I42cc5b8736e73728c5deec6349e8d2a814e19e83
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16281
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Omar Pakker
Diffstat (limited to 'src/southbridge/nvidia')
| -rw-r--r-- | src/southbridge/nvidia/ck804/ide.c | 2 | ||||
| -rw-r--r-- | src/southbridge/nvidia/ck804/lpc.c | 2 | ||||
| -rw-r--r-- | src/southbridge/nvidia/ck804/sata.c | 2 | ||||
| -rw-r--r-- | src/southbridge/nvidia/mcp55/ide.c | 2 | ||||
| -rw-r--r-- | src/southbridge/nvidia/mcp55/sata.c | 6 |
5 files changed, 7 insertions, 7 deletions
diff --git a/src/southbridge/nvidia/ck804/ide.c b/src/southbridge/nvidia/ck804/ide.c index 8914f2a329..a4b5475ca0 100644 --- a/src/southbridge/nvidia/ck804/ide.c +++ b/src/southbridge/nvidia/ck804/ide.c @@ -36,7 +36,7 @@ static void ide_init(struct device *dev) if (conf->ide1_enable) { /* Enable secondary IDE interface. */ word |= (1 << 0); - printk(BIOS_DEBUG, "IDE1 \t"); + printk(BIOS_DEBUG, "IDE1\t"); } if (conf->ide0_enable) { /* Enable primary IDE interface. */ diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 34e24f1c34..d15ef8e178 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -111,7 +111,7 @@ static void lpc_init(device_t dev) lpc_common_init(dev); pm_base = pci_read_config32(dev, 0x60) & 0xff00; - printk(BIOS_INFO, "%s: pm_base = %x \n", __func__, pm_base); + printk(BIOS_INFO, "%s: pm_base = %x\n", __func__, pm_base); /* Power after power fail */ on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; diff --git a/src/southbridge/nvidia/ck804/sata.c b/src/southbridge/nvidia/ck804/sata.c index eeebf897de..b67cf28aba 100644 --- a/src/southbridge/nvidia/ck804/sata.c +++ b/src/southbridge/nvidia/ck804/sata.c @@ -102,7 +102,7 @@ static void sata_init(struct device *dev) if (conf->sata1_enable) { /* Enable secondary SATA interface. */ dword |= (1 << 0); - printk(BIOS_DEBUG, "SATA S \t"); + printk(BIOS_DEBUG, "SATA S\t"); } if (conf->sata0_enable) { /* Enable primary SATA interface. */ diff --git a/src/southbridge/nvidia/mcp55/ide.c b/src/southbridge/nvidia/mcp55/ide.c index 4e618742e0..797b9d8780 100644 --- a/src/southbridge/nvidia/mcp55/ide.c +++ b/src/southbridge/nvidia/mcp55/ide.c @@ -38,7 +38,7 @@ static void ide_init(struct device *dev) if (conf->ide1_enable) { /* Enable secondary IDE interface. */ word |= (1 << 0); - printk(BIOS_DEBUG, "IDE1 \t"); + printk(BIOS_DEBUG, "IDE1\t"); } if (conf->ide0_enable) { /* Enable primary IDE interface. */ diff --git a/src/southbridge/nvidia/mcp55/sata.c b/src/southbridge/nvidia/mcp55/sata.c index 78cd27a978..fa761d2ffd 100644 --- a/src/southbridge/nvidia/mcp55/sata.c +++ b/src/southbridge/nvidia/mcp55/sata.c @@ -39,16 +39,16 @@ static void sata_init(struct device *dev) if (conf->sata1_enable) { /* Enable secondary SATA interface */ dword |= (1<<0); - printk(BIOS_DEBUG, "SATA S \t"); + printk(BIOS_DEBUG, "SATA S\t"); } if (conf->sata0_enable) { /* Enable primary SATA interface */ dword |= (1<<1); - printk(BIOS_DEBUG, "SATA P \n"); + printk(BIOS_DEBUG, "SATA P\n"); } } else { dword |= (1<<1) | (1<<0); - printk(BIOS_DEBUG, "SATA P and S \n"); + printk(BIOS_DEBUG, "SATA P and S\n"); } |